[PATCH 6/9] clk: mediatek: mt7629: convert to mtk_gate_clk_data

[Julien Stephan]

MT7629 currently declares a separate U_BOOT_DRIVER and probe()
function for each clock gate controller, despite all of them sharing
the same implementation.

Convert MT7629 to use the generic mtk_gate_clk_data infrastructure so
that all clock gate controllers share a single probe() function.
infracfg and pericfg, which are both bound before relocation, are
merged into a single driver, as are sgmiisys and ssusbsys. ethsys
keeps its own U_BOOT_DRIVER since it additionally binds a reset
controller.

Note that this also fixes the gate lookup of infracfg: its clock IDs
start at CLK_INFRA_DBGCLK_PD (1), but the driver passed a gate offset
of 0 to mtk_common_clk_gate_init(), so any infracfg gate request
(e.g. CLK_INFRA_TRNG_PD, referenced by the rng node) resolved to the
wrong gate. The generic probe() derives the offset from the ID of the
first gate in the table, which is correct for all controllers.

Signed-off-by: Julien Stephan <jstephan at baylibre.com>
---
 drivers/clk/mediatek/clk-mt7629.c | 109 +++++++++++++++-----------------------
 1 file changed, 42 insertions(+), 67 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
index aee340aeb37..11c6de2718b 100644
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -641,22 +641,15 @@ static int mt7629_topckgen_probe(struct udevice *dev)
 	return mtk_common_clk_init(dev, &mt7629_topckgen_clk_tree);
 }
 
-static int mt7629_infracfg_probe(struct udevice *dev)
+static int mt7629_clk_gate_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, infra_cgs,
-					ARRAY_SIZE(infra_cgs), 0);
-}
+	struct mtk_gate_clk_data *data;
 
-static int mt7629_pericfg_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, peri_cgs,
-					ARRAY_SIZE(peri_cgs), CLK_PERI_PWM1_PD);
-}
+	data = (void *)dev_get_driver_data(dev);
 
-static int mt7629_ethsys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, eth_cgs,
-					ARRAY_SIZE(eth_cgs), 0);
+	return mtk_common_clk_gate_init(dev, &mt7629_clk_tree,
+					data->gates, data->num_gates,
+					data->gates[0].id);
 }
 
 static int mt7629_ethsys_bind(struct udevice *dev)
@@ -672,18 +665,6 @@ static int mt7629_ethsys_bind(struct udevice *dev)
 	return ret;
 }
 
-static int mt7629_sgmiisys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs,
-					ARRAY_SIZE(sgmii_cgs), 0);
-}
-
-static int mt7629_ssusbsys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, ssusb_cgs,
-					ARRAY_SIZE(ssusb_cgs), 0);
-}
-
 static const struct udevice_id mt7629_apmixed_compat[] = {
 	{ .compatible = "mediatek,mt7629-apmixedsys" },
 	{ }
@@ -694,28 +675,41 @@ static const struct udevice_id mt7629_topckgen_compat[] = {
 	{ }
 };
 
-static const struct udevice_id mt7629_infracfg_compat[] = {
-	{ .compatible = "mediatek,mt7629-infracfg", },
-	{ }
-};
-
-static const struct udevice_id mt7629_pericfg_compat[] = {
-	{ .compatible = "mediatek,mt7629-pericfg", },
+MTK_GATE_CLK_DATA(infra_cgs);
+MTK_GATE_CLK_DATA(peri_cgs);
+static const struct udevice_id mt7629_clk_gate_compat[] = {
+	{
+		.compatible = "mediatek,mt7629-infracfg",
+		.data = (ulong)&infra_cgs_data
+	},
+	{
+		.compatible = "mediatek,mt7629-pericfg",
+		.data = (ulong)&peri_cgs_data
+	},
 	{ }
 };
 
+MTK_GATE_CLK_DATA(eth_cgs);
 static const struct udevice_id mt7629_ethsys_compat[] = {
-	{ .compatible = "mediatek,mt7629-ethsys", },
+	{
+		.compatible = "mediatek,mt7629-ethsys",
+		.data = (ulong)&eth_cgs_data
+	},
 	{ }
 };
 
-static const struct udevice_id mt7629_sgmiisys_compat[] = {
-	{ .compatible = "mediatek,mt7629-sgmiisys", },
-	{ }
-};
+MTK_GATE_CLK_DATA(sgmii_cgs);
+MTK_GATE_CLK_DATA(ssusb_cgs);
 
-static const struct udevice_id mt7629_ssusbsys_compat[] = {
-	{ .compatible = "mediatek,mt7629-ssusbsys" },
+static const struct udevice_id mt7629_clk_gate_phy_compat[] = {
+	{
+		.compatible = "mediatek,mt7629-sgmiisys",
+		.data = (ulong)&sgmii_cgs_data
+	},
+	{
+		.compatible = "mediatek,mt7629-ssusbsys",
+		.data = (ulong)&ssusb_cgs_data
+	},
 	{ }
 };
 
@@ -754,21 +748,11 @@ U_BOOT_DRIVER(mt7629_clk_topckgen) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mt7629_clk_infracfg) = {
-	.name = "mt7629-clock-infracfg",
+U_BOOT_DRIVER(mt7629_clk_gate) = {
+	.name = "mt7629-gate-clk",
 	.id = UCLASS_CLK,
-	.of_match = mt7629_infracfg_compat,
-	.probe = mt7629_infracfg_probe,
-	.priv_auto	= sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
-	.flags = DM_FLAG_PRE_RELOC,
-};
-
-U_BOOT_DRIVER(mt7629_clk_pericfg) = {
-	.name = "mt7629-clock-pericfg",
-	.id = UCLASS_CLK,
-	.of_match = mt7629_pericfg_compat,
-	.probe = mt7629_pericfg_probe,
+	.of_match = mt7629_clk_gate_compat,
+	.probe = mt7629_clk_gate_probe,
 	.priv_auto	= sizeof(struct mtk_cg_priv),
 	.ops = &mtk_clk_gate_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -778,26 +762,17 @@ U_BOOT_DRIVER(mt7629_clk_ethsys) = {
 	.name = "mt7629-clock-ethsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7629_ethsys_compat,
-	.probe = mt7629_ethsys_probe,
+	.probe = mt7629_clk_gate_probe,
 	.bind = mt7629_ethsys_bind,
 	.priv_auto	= sizeof(struct mtk_cg_priv),
 	.ops = &mtk_clk_gate_ops,
 };
 
-U_BOOT_DRIVER(mt7629_clk_sgmiisys) = {
-	.name = "mt7629-clock-sgmiisys",
-	.id = UCLASS_CLK,
-	.of_match = mt7629_sgmiisys_compat,
-	.probe = mt7629_sgmiisys_probe,
-	.priv_auto	= sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
-};
-
-U_BOOT_DRIVER(mt7629_clk_ssusbsys) = {
-	.name = "mt7629-clock-ssusbsys",
+U_BOOT_DRIVER(mt7629_clk_gate_phy) = {
+	.name = "mt7629-gate-clk-phy",
 	.id = UCLASS_CLK,
-	.of_match = mt7629_ssusbsys_compat,
-	.probe = mt7629_ssusbsys_probe,
+	.of_match = mt7629_clk_gate_phy_compat,
+	.probe = mt7629_clk_gate_probe,
 	.priv_auto	= sizeof(struct mtk_cg_priv),
 	.ops = &mtk_clk_gate_ops,
 };

-- 
2.54.0