[PATCH v1 1/3] net: fsl_enetc_xpcs_phy: Extract common PMA MMD init sequence into helper function
alice.guo at oss.nxp.com
alice.guo at oss.nxp.com
Wed Jun 3 12:51:50 CEST 2026
From: Alice Guo <alice.guo at nxp.com>
Extract steps 1.6-1.13 of PMA MMD initialization from
xpcs_phy_usxgmii_pma_config() into xpcs_phy_common_init_seq_1_pma() to
improve code reusability.
No functional changes.
Signed-off-by: Alice Guo <alice.guo at nxp.com>
---
drivers/net/fsl_enetc_xpcs_phy.c | 181 +++++++++++++++++++++------------------
1 file changed, 99 insertions(+), 82 deletions(-)
diff --git a/drivers/net/fsl_enetc_xpcs_phy.c b/drivers/net/fsl_enetc_xpcs_phy.c
index 4039690223d..9c1ee752a66 100644
--- a/drivers/net/fsl_enetc_xpcs_phy.c
+++ b/drivers/net/fsl_enetc_xpcs_phy.c
@@ -261,6 +261,100 @@ int xpcs_phy_write_pma(struct udevice *dev, int reg, u16 val)
return xpcs_write(dev, MDIO_MMD_PMAPMD, XPCS_PHY_REG(reg), val);
}
+static int xpcs_phy_common_init_seq_1_pma(struct udevice *dev)
+{
+ ulong begin;
+ u16 val;
+
+ /* 1.6 Turn off C37 auto-negotiation */
+ val = xpcs_read(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_CTRL));
+ val &= ~MII_CTRL_AN_ENABLE;
+ xpcs_write(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_CTRL), val);
+
+ /* 1.7 Assert tx_reset and rx_reset */
+ val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0);
+ val |= PMA_TX_GENCTRL0_TX_RST_0;
+ xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val);
+
+ val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1);
+ val |= PMA_RX_GENCTRL1_RX_RST_0;
+ xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val);
+
+ /* 1.8 Wait for more than 1us */
+ udelay(5);
+
+ /* 1.9 Deassert tx_reset and rx_reset */
+ val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0);
+ val &= ~PMA_TX_GENCTRL0_TX_RST_0;
+ xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val);
+
+ val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1);
+ val &= ~PMA_RX_GENCTRL1_RX_RST_0;
+ xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val);
+
+ /* 1.10 Power down MPLL */
+ val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL);
+ val = u16_replace_bits(val, 3, PMA_POWER_STATE_CTRL_TX0_PSTATE_MASK);
+ xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL, val);
+
+ val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL);
+ val &= ~PMA_MPLL_CMN_CTRL_MPLL_EN_0;
+ xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, val);
+
+ val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0);
+ val &= ~PMA_TX_GENCTRL0_TX_DT_EN_0;
+ xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val);
+
+ /* 1.11 Change RX0 power state to P2 */
+ val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0);
+ val &= ~PMA_RX_GENCTRL0_RX_DT_EN_0;
+ xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0, val);
+
+ /* TODO: check if it is needed */
+ val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL);
+ val = u16_replace_bits(val, 1, PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK);
+ xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val);
+
+ val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL);
+ val = u16_replace_bits(val, 3, PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK);
+ xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val);
+
+ /* 1.12 Assert request of transmit and receive */
+ val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);
+ val |= PMA_TX_GENCTRL2_TX_REQ_0;
+ xpcs_phy_write_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2, val);
+
+ val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);
+ val |= PMA_RX_GENCTRL2_RX_REQ_0;
+ xpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val);
+
+ /* 1.13 Poll for acknlowledge */
+ begin = get_timer(0);
+ do {
+ val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);
+ if (get_timer(begin) > 500) {
+ dev_err(dev, "Polling timeout, line: %d\n", __LINE__);
+ goto timeout;
+ }
+ mdelay(10);
+ } while (val & PMA_TX_GENCTRL2_TX_REQ_0);
+
+ begin = get_timer(0);
+ do {
+ val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);
+ if (get_timer(begin) > 500) {
+ dev_err(dev, "Polling timeout, line: %d\n", __LINE__);
+ goto timeout;
+ }
+ mdelay(10);
+ } while (val & PMA_RX_GENCTRL2_RX_REQ_0);
+
+ return 0;
+
+timeout:
+ return -ETIMEDOUT;
+}
+
int xpcs_phy_usxgmii_init_seq_2(struct udevice *dev)
{
ulong begin;
@@ -436,93 +530,16 @@ timeout:
int xpcs_phy_usxgmii_pma_config(struct udevice *dev)
{
+ int ret;
ulong begin;
u16 val;
xpcs_phy_reg_lock(dev);
- /* 1.6 Turn off C37 auto-negotiation */
- val = xpcs_read(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_CTRL));
- val &= ~MII_CTRL_AN_ENABLE;
- xpcs_write(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_CTRL), val);
-
- /* 1.7 Assert tx_reset and rx_reset*/
- val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0);
- val |= PMA_TX_GENCTRL0_TX_RST_0;
- xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val);
-
- val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1);
- val |= PMA_RX_GENCTRL1_RX_RST_0;
- xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val);
-
- /* 1.8 Wait for more than 1us */
- udelay(5);
-
- /* 1.9 Deassert tx_reset and rx_reset*/
- val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0);
- val &= ~PMA_TX_GENCTRL0_TX_RST_0;
- xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val);
-
- val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1);
- val &= ~PMA_RX_GENCTRL1_RX_RST_0;
- xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val);
-
- /* 1.10 Power down MPLLA */
- val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL);
- val = u16_replace_bits(val, 3, PMA_POWER_STATE_CTRL_TX0_PSTATE_MASK);
- xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL, val);
-
- val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL);
- val &= ~PMA_MPLL_CMN_CTRL_MPLL_EN_0;
- xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, val);
-
- val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0);
- val &= ~PMA_TX_GENCTRL0_TX_DT_EN_0;
- xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val);
-
- /* 1.11 Change RX0 power state to P2 */
- val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0);
- val &= ~PMA_RX_GENCTRL0_RX_DT_EN_0;
- xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0, val);
-
- /* TODO: check if it is needed */
- val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL);
- val = u16_replace_bits(val, 1, PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK);
- xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val);
-
- val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL);
- val = u16_replace_bits(val, 3, PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK);
- xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val);
-
- /* 1.12 Assert request of transmit and receive */
- val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);
- val |= PMA_TX_GENCTRL2_TX_REQ_0;
- xpcs_phy_write_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2, val);
-
- val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);
- val |= PMA_RX_GENCTRL2_RX_REQ_0;
- xpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val);
-
- /* 1.13 Poll for acknlowledge */
- begin = get_timer(0);
- do {
- val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);
- if (get_timer(begin) > 500) {
- dev_err(dev, "Polling timeout, line: %d\n", __LINE__);
- goto timeout;
- }
- mdelay(10);
- } while (val & PMA_TX_GENCTRL2_TX_REQ_0);
-
- begin = get_timer(0);
- do {
- val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);
- if (get_timer(begin) > 500) {
- dev_err(dev, "Polling timeout, line: %d\n", __LINE__);
- goto timeout;
- }
- mdelay(10);
- } while (val & PMA_RX_GENCTRL2_RX_REQ_0);
+ /* seq 1: reset, power down MPLL, assert REQ (USXGMII: AN disabled) */
+ ret = xpcs_phy_common_init_seq_1_pma(dev);
+ if (ret)
+ goto timeout;
/* 2 Config MPLL for 10G XGMII */
val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_REF_CLK_CTRL);
--
2.34.1
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