[PATCH 5/9] arm64: zynqmp: Add CMA reserved-memory for runtime FPGA loading
Michal Simek
michal.simek at amd.com
Tue Jun 9 09:48:19 CEST 2026
Add CMA (Contiguous Memory Allocator) reserved-memory regions to all
Xilinx arm64 board device trees to support runtime FPGA programming.
The CMA pool uses dynamic allocation constrained to the low 2 GB DDR region
via alloc-ranges so that the kernel places it within the 32-bit addressable
space.
CMA sizes are chosen per silicon family to accommodate the maximum PL
bitstream/PDI size:
- Kria K24 SOM: 64 MB
- ZynqMP boards: 128 MB
For Kria K24 SOM the CMA inherited from K26 is overridden to 64 MB.
For Kria SOMs, the CMA node is added to the SOM DTS only, not to
carrier board overlays.
Signed-off-by: Michal Simek <michal.simek at amd.com>
---
arch/arm/dts/zynqmp-sm-k24-revA.dts | 7 ++++++-
arch/arm/dts/zynqmp-sm-k26-revA.dts | 11 ++++++++++-
arch/arm/dts/zynqmp-zc1232-revA.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zc1254-revA.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 17 ++++++++++++++++-
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 17 ++++++++++++++++-
arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zcu100-revC.dts | 17 ++++++++++++++++-
arch/arm/dts/zynqmp-zcu102-revA.dts | 17 ++++++++++++++++-
arch/arm/dts/zynqmp-zcu104-revA.dts | 17 ++++++++++++++++-
arch/arm/dts/zynqmp-zcu104-revC.dts | 17 ++++++++++++++++-
arch/arm/dts/zynqmp-zcu106-revA.dts | 17 ++++++++++++++++-
arch/arm/dts/zynqmp-zcu111-revA.dts | 17 ++++++++++++++++-
arch/arm/dts/zynqmp-zcu1275-revA.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zcu1275-revB.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zcu1285-revA.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zcu208-revA.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zcu216-revA.dts | 15 +++++++++++++++
arch/arm/dts/zynqmp-zcu670-revA.dts | 17 ++++++++++++++++-
arch/arm/dts/zynqmp-zcu670-revB.dts | 17 ++++++++++++++++-
22 files changed, 326 insertions(+), 12 deletions(-)
diff --git a/arch/arm/dts/zynqmp-sm-k24-revA.dts b/arch/arm/dts/zynqmp-sm-k24-revA.dts
index 653bd9362264..34ee6af801de 100644
--- a/arch/arm/dts/zynqmp-sm-k24-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k24-revA.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP SM-K24 RevA
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
- * (C) Copyright 2022, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022-2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek at amd.com>
*/
@@ -21,3 +21,8 @@
reg = <0 0 0 0x80000000>;
};
};
+
+&cma {
+ size = <0x0 0x4000000>;
+ alignment = <0x0 0x4000000>;
+};
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index 0abec77b3f3a..c7fe253244f6 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
- * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek at amd.com>
*/
@@ -61,6 +61,15 @@
reg = <0x0 0x7ff00000 0x0 0x100000>;
no-map;
};
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
};
gpio-keys {
diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts
index 34e5b6edab10..f0e2a0b4588f 100644
--- a/arch/arm/dts/zynqmp-zc1232-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1232-revA.dts
@@ -31,6 +31,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
};
&dcc {
diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts
index 827143377b96..e92caefd3aa2 100644
--- a/arch/arm/dts/zynqmp-zc1254-revA.dts
+++ b/arch/arm/dts/zynqmp-zc1254-revA.dts
@@ -32,6 +32,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
};
&dcc {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index 33efdbf0e25e..2897c423f82e 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
*
* (C) Copyright 2015 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek at amd.com>
*/
@@ -41,6 +41,21 @@
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
clock_si5338_0: clk27 { /* u55 SI5338-GM */
compatible = "fixed-clock";
#clock-cells = <0>;
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index 13c304520a60..0b1185d862cd 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
*
* (C) Copyright 2015 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek at amd.com>
*/
@@ -39,6 +39,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
};
&can0 {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
index 796669fc92c0..bfcc92cedfad 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
@@ -39,6 +39,21 @@
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
clock_si5338_2: clk26 {
compatible = "fixed-clock";
#clock-cells = <0>;
diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
index cd80aed9a388..9b59952993f1 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -38,6 +38,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
};
&can0 {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index 53aa3dca1dca..722b2e833b44 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -37,6 +37,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
};
&fpd_dma_chan1 {
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index 4ec8a400494e..62f94da334db 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU100 revC
*
* (C) Copyright 2016 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek at amd.com>
* Nathalie Chan King Choy
@@ -47,6 +47,21 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
autorepeat;
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 9590dd1cd92a..a0ef866a259a 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU102 RevA
*
* (C) Copyright 2015 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek at amd.com>
*/
@@ -45,6 +45,21 @@
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
autorepeat;
diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts
index 3fe7cb410bcf..4479ff735145 100644
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU104
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek at amd.com>
*/
@@ -43,6 +43,21 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
clock_8t49n287_5: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts
index 21ce50e1da93..0caedc40a519 100644
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU104
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek at amd.com>
*/
@@ -43,6 +43,21 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
ina226 {
compatible = "iio-hwmon";
io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 0ac1472c55dd..c0bc46faee4e 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU106
*
* (C) Copyright 2016 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek at amd.com>
*/
@@ -45,6 +45,21 @@
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
autorepeat;
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index 7894daeca943..f38edd6145f5 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU111
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek at amd.com>
*/
@@ -45,6 +45,21 @@
/* Another 4GB connected to PL */
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
autorepeat;
diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts
index b9d51fadc2ab..1a49ae3ba4e4 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts
@@ -32,6 +32,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
};
&dcc {
diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts
index f26d9843243b..1b6f7a605d6f 100644
--- a/arch/arm/dts/zynqmp-zcu1275-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts
@@ -35,6 +35,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
};
&dcc {
diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts
index 86a3217f9ab6..b2d71f0f4556 100644
--- a/arch/arm/dts/zynqmp-zcu1285-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts
@@ -36,6 +36,21 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
};
&dcc {
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
index 70b1e81e304c..3c3c94dcadfc 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -43,6 +43,21 @@
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
autorepeat;
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index bc0ca24ff050..b0f0a74f711e 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -43,6 +43,21 @@
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
autorepeat;
diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts b/arch/arm/dts/zynqmp-zcu670-revA.dts
index 1215babe2146..c5b70972ef52 100644
--- a/arch/arm/dts/zynqmp-zcu670-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu670-revA.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU670 (67DR)
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek at amd.com>
*/
@@ -46,6 +46,21 @@
/* Another 4GB connected to PL */
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
autorepeat;
diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts b/arch/arm/dts/zynqmp-zcu670-revB.dts
index e91f280e4576..cd96a7a0d136 100644
--- a/arch/arm/dts/zynqmp-zcu670-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu670-revB.dts
@@ -3,7 +3,7 @@
* dts file for Xilinx ZynqMP ZCU670 (67DR) revB
*
* (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek at amd.com>
*/
@@ -46,6 +46,21 @@
/* Another 4GB connected to PL */
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x8000000>;
+ alignment = <0x0 0x8000000>;
+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+ linux,cma-default;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
autorepeat;
--
2.43.0
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