[PATCH 9/9] arm64: zynqmp: Sync compatible string format

[Michal Simek]

There is no reason to have non zynqmp-sc compatible string for overlays
which can be applied only with SCs.

Signed-off-by: Michal Simek <michal.simek at amd.com>
---

 arch/arm/dts/zynqmp-sc-vek280-revA.dtso | 5 ++---
 arch/arm/dts/zynqmp-sc-vek280-revB.dtso | 5 ++---
 arch/arm/dts/zynqmp-sc-vhk158-revA.dtso | 5 ++---
 arch/arm/dts/zynqmp-sc-vpk120-revB.dtso | 5 ++---
 arch/arm/dts/zynqmp-sc-vpk180-revA.dtso | 5 ++---
 arch/arm/dts/zynqmp-sc-vpk180-revB.dtso | 5 ++---
 6 files changed, 12 insertions(+), 18 deletions(-)

diff --git a/arch/arm/dts/zynqmp-sc-vek280-revA.dtso b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso
index e94b784e8e1f..7212ee9df86b 100644
--- a/arch/arm/dts/zynqmp-sc-vek280-revA.dtso
+++ b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP VEK280 revA
  *
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek at amd.com>
  */
@@ -13,8 +13,7 @@
 /plugin/;
 
 &{/} {
-	compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-vek280-revA",
-		     "xlnx,zynqmp-vek280", "xlnx,zynqmp";
+	compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-sc-vek280", "xlnx,zynqmp";
 
 	vc7_xin: vc7-xin {
 		compatible = "fixed-clock";
diff --git a/arch/arm/dts/zynqmp-sc-vek280-revB.dtso b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso
index a3983f330d07..a57e9b50b20c 100644
--- a/arch/arm/dts/zynqmp-sc-vek280-revB.dtso
+++ b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP VEK280 revB
  *
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek at amd.com>
  */
@@ -10,6 +10,5 @@
 #include "zynqmp-sc-vek280-revA.dtso"
 
 &{/} {
-	compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB",
-		     "xlnx,zynqmp-vek280", "xlnx,zynqmp";
+	compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-sc-vek280", "xlnx,zynqmp";
 };
diff --git a/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso
index fd25731b0b43..2fe35596143b 100644
--- a/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso
+++ b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP VHK158 revA
  *
  * (C) Copyright 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek at amd.com>
  */
@@ -14,8 +14,7 @@
 /plugin/;
 
 &{/} {
-	compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-vhk158-revA",
-		     "xlnx,zynqmp-vhk158", "xlnx,zynqmp";
+	compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-sc-vhk158", "xlnx,zynqmp";
 
 	vc7_xin: vc7-xin {
 		compatible = "fixed-clock";
diff --git a/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso
index 29b3a73fde01..ae0691c01271 100644
--- a/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso
+++ b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP VPK120 revB
  *
  * (C) Copyright 2021 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek at amd.com>
  */
@@ -14,8 +14,7 @@
 /plugin/;
 
 &{/} {
-	compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-vpk120-revB",
-		     "xlnx,zynqmp-vpk120", "xlnx,zynqmp";
+	compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-sc-vpk120", "xlnx,zynqmp";
 };
 
 &i2c0 {
diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
index 10466ce99de6..9b6534f6383c 100644
--- a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
+++ b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP VPK180 revA
  *
  * (C) Copyright 2021 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek at amd.com>
  */
@@ -14,8 +14,7 @@
 /plugin/;
 
 &{/} {
-	compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-vpk180-revA",
-		     "xlnx,zynqmp-vpk180", "xlnx,zynqmp";
+	compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-sc-vpk180", "xlnx,zynqmp";
 
 	vc7_xin: vc7-xin {
 		compatible = "fixed-clock";
diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
index 6a5ada34ed71..941d26c025a8 100644
--- a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
+++ b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso
@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP VPK180 revB
  *
  * (C) Copyright 2021 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek at amd.com>
  */
@@ -14,8 +14,7 @@
 /plugin/;
 
 &{/} {
-	compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-vpk180-revB",
-		     "xlnx,zynqmp-vpk180", "xlnx,zynqmp";
+	compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-sc-vpk180", "xlnx,zynqmp";
 
 	vc7_xin: vc7-xin {
 		compatible = "fixed-clock";
-- 
2.43.0