[PATCH v3 2/4] pci: pcie_dw_rockchip: enable clocks before PHY init

[Heiko Stübner]

Am Mittwoch, 20. Mai 2026, 08:05:28 Mitteleuropäische Sommerzeit schrieb Daniele Briguglio:
> rockchip_pcie_init_port() calls generic_phy_init() and
> generic_phy_power_on() before clk_enable_bulk(), so the PCIe PHY
> tries to lock its PLL while the external reference clock can still
> be off.  Where the refclk is generated by an external oscillator
> gated by a regulator that is not marked regulator-always-on (e.g.
> the PI6C clock generator on radxa rock-3b modelled with the
> gated-fixed-clock binding), this results in a PHY lock timeout:
> 
>   rockchip_pcie3phy phy at fe8c0000: lock failed 0x6890000
>   rockchip_pcie3phy phy at fe8c0000: PHY: Failed to init phy at fe8c0000: -110.
>   pcie_dw_rockchip pcie at fe280000: failed to init phy (ret=-110)
> 
> Move clk_enable_bulk() ahead of generic_phy_init() so that any
> clock-frequency consumer (including external gated refclks) is
> powered up before the PHY PLL attempts to lock.
> 
> Reported-by: Jonas Karlman <jonas at kwiboo.se>
> Signed-off-by: Daniele Briguglio <hello at superkali.me>

Reviewed-by: Heiko Stuebner <heiko at sntech.de>
Tested-by: Heiko Stuebner <heiko at sntech.de> # rock-5-itx