[PATCH v4 4/9] arm: socfpga: Update Stratix10 SPL data save and restore implementation

[Chee, Tien Fong]

On 5/6/2026 9:54 am, alif.zakuan.yuslaimi at altera.com wrote:
> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
>
> Enable backup for data section to support warm reset in Stratix10 SPL as
> no SPL image would be reloaded in warm reset.
>
> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
> ---
>
> Changes in v4:
> - Update reset_flag() weak function to take in u32 flag parameter
>
>   arch/arm/mach-socfpga/spl_s10.c     | 17 +++++++++++++++++
>   configs/socfpga_stratix10_defconfig |  2 +-
>   2 files changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
> index 8ab80740c6e..00d43460fce 100644
> --- a/arch/arm/mach-socfpga/spl_s10.c
> +++ b/arch/arm/mach-socfpga/spl_s10.c
> @@ -21,12 +21,29 @@
>   #include <watchdog.h>
>   #include <dm/uclass.h>
>   
> +u32 reset_flag(u32 flag)
> +{
> +	/* Check rstmgr.stat for warm reset status */
> +	u32 status = readl(SOCFPGA_RSTMGR_ADDRESS);
> +
> +	/* Check whether any L4 watchdogs or SDM had triggered warm reset */
> +	u32 warm_reset_mask = RSTMGR_L4WD_MPU_WARMRESET_MASK;
> +
> +	if (status & warm_reset_mask)
> +		return 0;
> +
> +	return 1;
> +}
> +
>   void board_init_f(ulong dummy)
>   {
>   	const struct cm_config *cm_default_cfg = cm_get_default_config();
>   	int ret;
>   	struct udevice *dev;
>   
> +	if (IS_ENABLED(CONFIG_XPL_BUILD))
> +		spl_save_restore_data();
> +
>   	ret = spl_early_init();
>   	if (ret)
>   		hang();
> diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
> index 82f0cceafb4..be0c452ead0 100644
> --- a/configs/socfpga_stratix10_defconfig
> +++ b/configs/socfpga_stratix10_defconfig
> @@ -3,7 +3,6 @@ CONFIG_COUNTER_FREQUENCY=400000000
>   CONFIG_ARCH_SOCFPGA=y
>   CONFIG_TEXT_BASE=0x200000
>   CONFIG_NR_DRAM_BANKS=2
> -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
>   CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>   CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
>   CONFIG_SF_DEFAULT_MODE=0x2003
> @@ -19,6 +18,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x100000
>   CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
>   CONFIG_IDENT_STRING="socfpga_stratix10"
>   CONFIG_SPL_FS_FAT=y
> +CONFIG_SPL_RECOVER_DATA_SECTION=y
>   CONFIG_FIT=y
>   CONFIG_SPL_FIT_SIGNATURE=y
>   CONFIG_SPL_LOAD_FIT=y


Reviewed-by: Tien Fong Chee <tien.fong.chee at altera.com>

Best regards,
Tien Fong