[PATCH v4 8/9] mmc: socfpga_dw_mmc: Exclude S10 from legacy clkmgr address retrieval

[Chee, Tien Fong]

On 5/6/2026 9:55 am, alif.zakuan.yuslaimi at altera.com wrote:
> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
>
> Excluding Stratix10 from legacy implementation of retrieving clkmgr base
> address as Stratix10's clock driver is already following clock driver model
> and is supporting enable/disable APIs.
>
> The legacy devices' clock driver will continue to be refactored to support
> driver model which enables us to support enable/disable APIs for all these
> devices.
>
> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
> ---
>
> (no changes since v1)
>
>   drivers/mmc/socfpga_dw_mmc.c | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
> index c8da6ead0ea..b12212e02dd 100644
> --- a/drivers/mmc/socfpga_dw_mmc.c
> +++ b/drivers/mmc/socfpga_dw_mmc.c
> @@ -59,7 +59,8 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host)
>   			 ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
>   
>   	if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) &&
> -	    !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)) {
> +	    !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) &&
> +	    !IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10)) {
>   		/* Disable SDMMC clock. */
>   		clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
>   			     CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
> @@ -96,7 +97,8 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host)
>   #endif
>   
>   	if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) &&
> -	    !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)) {
> +	    !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) &&
> +	    !IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10)) {
>   		/* Enable SDMMC clock */
>   		setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
>   			     CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);


Reviewed-by: Tien Fong Chee <tien.fong.chee at altera.com>

Best regards,
Tien Fong