[PATCH v4 2/7] mtd: spi-nor-ids: Add support for ESMT/EON EN25QX128A/EN25QH256/EN25QX256A

[Takahiro.Kuwano at infineon.com]

Hi,

> 
> EN25QX128A/EN25QX256A are 128Mb/256Mb flash devices with Quad interface at
> max 104MHz clock rate.
> EN25QH256 is 256Mb flash device with Quad interface at max 50MHz clock rate.
> Both flashes supports 2.7-3.6V voltage range.
> 
> These flashes are tested on MediaTek's filogic platform.
> 
> Link: https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25QX128A(2V).pdf
> Link: https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25QH256A(2R).pdf
> Signed-off-by: Weijie Gao <weijie.gao at mediatek.com>
> ---
> v2-v4: updated commit message
> ---
>  drivers/mtd/spi/spi-nor-core.c | 1 +
>  drivers/mtd/spi/spi-nor-ids.c  | 5 +++++
>  include/linux/mtd/spi-nor.h    | 1 +
>  3 files changed, 7 insertions(+)
> 
> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> index 937d79af64e..e4f78e740ba 100644
> --- a/drivers/mtd/spi/spi-nor-core.c
> +++ b/drivers/mtd/spi/spi-nor-core.c
> @@ -758,6 +758,7 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
>         case SNOR_MFR_ISSI:
>         case SNOR_MFR_MACRONIX:
>         case SNOR_MFR_WINBOND:
> +       case SNOR_MFR_EON:
>                 if (need_wren)
>                         write_enable(nor);
> 
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index 7d96adab4fd..fcc546fb5ae 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -95,6 +95,11 @@ const struct flash_info spi_nor_ids[] = {
>         { INFO("en25q64",    0x1c3017, 0, 64 * 1024,  128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>         { INFO("en25q128b",  0x1c3018, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>         { INFO("en25qh128",  0x1c7018, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> +       { INFO("en25qx128a", 0x1c7118, 0, 64 * 1024,  256,
> +              SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },

I have noticed that lock feature is only available for ST/Micron/SST chips now.
(please double-check, sorry if I missed something...)
If you need lock feature for EON chips, please test it and add EON to lock
support.

> +       { INFO("en25qh256",  0x1c7019, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> +       { INFO("en25qx256a", 0x1c7119, 0, 64 * 1024,  512,
> +              SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },

Same here.

>         { INFO("en25s64",    0x1c3817, 0, 64 * 1024,  128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>  #endif
>  #ifdef CONFIG_SPI_FRAM_FUJITSU
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index 4eef4ab0488..02fa72fb401 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -33,6 +33,7 @@
>  #define SNOR_MFR_SST           CFI_MFR_SST
>  #define SNOR_MFR_WINBOND       0xef /* Also used by some Spansion */
>  #define SNOR_MFR_CYPRESS       0x34
> +#define SNOR_MFR_EON           CFI_MFR_EON
> 
>  /*
>   * Note on opcode nomenclature: some opcodes have a format like
> --
> 2.45.2

Thanks,
Takahiro