[PATCH v4 7/7] mtd: spi-nor-ids: Add support for Winbond W25Q256JV-M/W25Q512JV-M

[Weijie Gao]

On Thu, 2026-06-11 at 03:01 +0000, Takahiro.Kuwano at infineon.com wrote:
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> 
> Hi,
> 
> > 
> > W25Q256JV-M/W25Q512JV-M are 256Mb/512Mb flash devices with Quad
> > interface at
> > max 104MHz clock rate. DTR is not supported.
> > These flashes supports 2.7-3.6V voltage range.
> > 
> > Both tested on MediaTek's filogic platform.
> > 
> > Link: 
> > https://urldefense.com/v3/__https://www.winbond.com/resource-files/W25Q256JV*20DTR*20RevK*2010202025*20Plus.pdf__;JSUlJQ!!CTRNKA9wMg0ARbw!igFctdFJEjSnYCT52waw-qrNxt1fsqf-t3PAZM90vZDff7jGE2ulb3s6ORLw7r3l779LqaDgTJnj6zv73BVVRnwP4U6h3Bk$
> > Link: 
> > https://urldefense.com/v3/__https://www.winbond.com/resource-files/W25Q512JV*20DTR*20RevD*2006292020*20133.pdf__;JSUlJQ!!CTRNKA9wMg0ARbw!igFctdFJEjSnYCT52waw-qrNxt1fsqf-t3PAZM90vZDff7jGE2ulb3s6ORLw7r3l779LqaDgTJnj6zv73BVVRnwPZFlwJQ8$
> > Signed-off-by: Weijie Gao <weijie.gao at mediatek.com>
> > ---
> > v3-v4: updated commit message
> > v2: refactored with previous patch. updated commit message
> > ---
> >  drivers/mtd/spi/spi-nor-ids.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-
> > nor-ids.c
> > index 3c183650229..dcb217f2401 100644
> > --- a/drivers/mtd/spi/spi-nor-ids.c
> > +++ b/drivers/mtd/spi/spi-nor-ids.c
> > @@ -585,6 +585,10 @@ const struct flash_info spi_nor_ids[] = {
> >                SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> > SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
> >         { INFO("w25q128jv-m", 0xef7018, 0, 64 * 1024, 256,
> >                SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> > SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
> > +       { INFO("w25q256jv-m", 0xef7019, 0, 64 * 1024, 512,
> > +              SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> > SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
> > +       { INFO("w25q512jv-m", 0xef7020, 0, 64 * 1024, 1024,
> > +              SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> > SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
> 
> Same as EON chip case in another patch.
> Looks like this issue existed in the first place. We need to rework
> lock
> feature to support other vendors' chips.

As the locking feature is not used by our platform, I think it's better
to remove these flags for now.

> 
> >         { INFO("w25q01jv-m", 0xef7021, 0, 64 * 1024, 2048,
> >                SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> > SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
> >         { INFO("w25q02jv-m", 0xef7022, 0, 64 * 1024, 4096,
> > --
> > 2.45.2
> 
> Thanks,
> Takahiro
>