[PATCH v1] serial: lpuart: Fix RX FIFO Enable bitmask

[Tom Rini]

On Thu, 28 May 2026 15:49:06 +0200, Emanuele Ghidoli wrote:

> The Receive FIFO Enable (RXFE) field in the LPUART FIFO register is
> bit 3 on all supported architectures. The define has been wrong since
> it was introduced: for non-i.MX8/i.MXRT it set bit 6, which on LS102xA
> is read-only-as-zero, so the bug went unnoticed.
> 
> NXP confirmed bit 3 is correct everywhere, so drop the ARCH-based
> selection.
> 
> [...]

Applied to u-boot/next, thanks!

[1/1] serial: lpuart: Fix RX FIFO Enable bitmask
      commit: e65a87e959166e250a486b67ca23270272741643
-- 
Tom