[PATCH v1 1/8] arm64: dts: qcom: add initial Shikra device tree support
Aswin Murugan
aswin.murugan at oss.qualcomm.com
Mon Jun 15 14:18:21 CEST 2026
Add initial device tree support for the Qualcomm Shikra SoC,
covering CQ2390M, CQ2390S and IQ2390S SoMs along with their
respective EVK boards.
This includes SoC DTSI, SoM-specific DTSI files with PMIC
regulator definitions, and EVK DTS files enabling basic
peripherals.
The content is ported from a device tree series submitted to
the Linux kernel [1], where support is not yet available
upstream.
[1] https://lore.kernel.org/all/20260527-shikra-dt-v4-0-b5ca1fa0b392@oss.qualcomm.com/
Signed-off-by: Aswin Murugan <aswin.murugan at oss.qualcomm.com>
---
arch/arm/dts/Makefile | 5 +
arch/arm/dts/shikra-cqm-evk.dts | 40 +
arch/arm/dts/shikra-cqm-som.dtsi | 156 ++++
arch/arm/dts/shikra-cqs-evk.dts | 40 +
arch/arm/dts/shikra-evk.dtsi | 14 +
arch/arm/dts/shikra-iqs-evk.dts | 40 +
arch/arm/dts/shikra-iqs-som.dtsi | 170 ++++
arch/arm/dts/shikra.dtsi | 842 ++++++++++++++++++
include/dt-bindings/clock/qcom,shikra-gcc.h | 262 ++++++
.../dt-bindings/interconnect/qcom,shikra.h | 121 +++
10 files changed, 1690 insertions(+)
create mode 100644 arch/arm/dts/shikra-cqm-evk.dts
create mode 100644 arch/arm/dts/shikra-cqm-som.dtsi
create mode 100644 arch/arm/dts/shikra-cqs-evk.dts
create mode 100644 arch/arm/dts/shikra-evk.dtsi
create mode 100644 arch/arm/dts/shikra-iqs-evk.dts
create mode 100644 arch/arm/dts/shikra-iqs-som.dtsi
create mode 100644 arch/arm/dts/shikra.dtsi
create mode 100644 include/dt-bindings/clock/qcom,shikra-gcc.h
create mode 100644 include/dt-bindings/interconnect/qcom,shikra.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2b65cd9105c..48f31888fcd 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -515,6 +515,11 @@ dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
+dtb-$(CONFIG_ARCH_SNAPDRAGON) += \
+ shikra-cqm-evk.dtb \
+ shikra-cqs-evk.dtb \
+ shikra-iqs-evk.dtb
+
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-inet-3f.dtb \
sun4i-a10-inet-3w.dtb
diff --git a/arch/arm/dts/shikra-cqm-evk.dts b/arch/arm/dts/shikra-cqm-evk.dts
new file mode 100644
index 00000000000..0a52ab9b7a4
--- /dev/null
+++ b/arch/arm/dts/shikra-cqm-evk.dts
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+
+#include "shikra-cqm-som.dtsi"
+#include "shikra-evk.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Shikra CQM EVK";
+ compatible = "qcom,shikra-cqm-evk", "qcom,shikra-cqm-som", "qcom,shikra";
+ chassis-type = "embedded";
+
+ aliases {
+ mmc0 = &sdhc_1;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&sdhc_1 {
+ vmmc-supply = <&pm4125_l20>;
+ vqmmc-supply = <&pm4125_l14>;
+
+ pinctrl-0 = <&sdc1_state_on>;
+ pinctrl-1 = <&sdc1_state_off>;
+ pinctrl-names = "default", "sleep";
+
+ non-removable;
+ supports-cqe;
+ no-sdio;
+ no-sd;
+
+ status = "okay";
+};
diff --git a/arch/arm/dts/shikra-cqm-som.dtsi b/arch/arm/dts/shikra-cqm-som.dtsi
new file mode 100644
index 00000000000..97966cff889
--- /dev/null
+++ b/arch/arm/dts/shikra-cqm-som.dtsi
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+#include "shikra.dtsi"
+#include "pm4125.dtsi"
+#include "pm8005.dtsi"
+
+/ {
+ gpio-key {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vol_up_n>;
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&pm4125_gpios 9 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ wakeup-source;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+};
+
+&pm4125_gpios {
+ vol_up_n: vol-up-n-state {
+ pins = "gpio9";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+};
+
+&pm4125_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
+&pm8005_regulators {
+ status = "disabled";
+};
+
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-pm2250-regulators";
+
+ pm4125_s2: s2 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm4125_l3: l3 {
+ regulator-min-microvolt = <624000>;
+ regulator-max-microvolt = <650000>;
+ };
+
+ pm4125_l4: l4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ };
+
+ pm4125_l5: l5 {
+ regulator-min-microvolt = <1232000>;
+ regulator-max-microvolt = <1304000>;
+ };
+
+ pm4125_l6: l6 {
+ regulator-min-microvolt = <788000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm4125_l7: l7 {
+ regulator-min-microvolt = <664000>;
+ regulator-max-microvolt = <664000>;
+ };
+
+ pm4125_l8: l8 {
+ regulator-min-microvolt = <928000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ pm4125_l9: l9 {
+ regulator-min-microvolt = <875000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ pm4125_l10: l10 {
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ };
+
+ pm4125_l12: l12 {
+ regulator-min-microvolt = <928000>;
+ regulator-max-microvolt = <975000>;
+ };
+
+ pm4125_l13: l13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm4125_l14: l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm4125_l15: l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm4125_l16: l16 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm4125_l17: l17 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3544000>;
+ };
+
+ pm4125_l18: l18 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ };
+
+ pm4125_l19: l19 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ };
+
+ pm4125_l20: l20 {
+ regulator-min-microvolt = <2952000>;
+ regulator-max-microvolt = <2952000>;
+ };
+
+ pm4125_l21: l21 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3056000>;
+ };
+
+ pm4125_l22: l22 {
+ regulator-min-microvolt = <3304000>;
+ regulator-max-microvolt = <3304000>;
+ };
+ };
+};
diff --git a/arch/arm/dts/shikra-cqs-evk.dts b/arch/arm/dts/shikra-cqs-evk.dts
new file mode 100644
index 00000000000..b3f19a64d7a
--- /dev/null
+++ b/arch/arm/dts/shikra-cqs-evk.dts
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+
+#include "shikra-cqm-som.dtsi"
+#include "shikra-evk.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Shikra CQS EVK";
+ compatible = "qcom,shikra-cqs-evk", "qcom,shikra-cqs-som", "qcom,shikra";
+ chassis-type = "embedded";
+
+ aliases {
+ mmc0 = &sdhc_1;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&sdhc_1 {
+ vmmc-supply = <&pm4125_l20>;
+ vqmmc-supply = <&pm4125_l14>;
+
+ pinctrl-0 = <&sdc1_state_on>;
+ pinctrl-1 = <&sdc1_state_off>;
+ pinctrl-names = "default", "sleep";
+
+ non-removable;
+ supports-cqe;
+ no-sdio;
+ no-sd;
+
+ status = "okay";
+};
diff --git a/arch/arm/dts/shikra-evk.dtsi b/arch/arm/dts/shikra-evk.dtsi
new file mode 100644
index 00000000000..6eb4184f764
--- /dev/null
+++ b/arch/arm/dts/shikra-evk.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+&qupv3_0 {
+ firmware-name = "qcom/shikra/qupv3fw.elf";
+
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/shikra-iqs-evk.dts b/arch/arm/dts/shikra-iqs-evk.dts
new file mode 100644
index 00000000000..3003a47bd75
--- /dev/null
+++ b/arch/arm/dts/shikra-iqs-evk.dts
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+
+#include "shikra-iqs-som.dtsi"
+#include "shikra-evk.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Shikra IQS EVK";
+ compatible = "qcom,shikra-iqs-evk", "qcom,shikra-iqs-som", "qcom,shikra";
+ chassis-type = "embedded";
+
+ aliases {
+ mmc0 = &sdhc_1;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&sdhc_1 {
+ vmmc-supply = <&pm8150_l17>;
+ vqmmc-supply = <&pm8150_s4>;
+
+ pinctrl-0 = <&sdc1_state_on>;
+ pinctrl-1 = <&sdc1_state_off>;
+ pinctrl-names = "default", "sleep";
+
+ non-removable;
+ supports-cqe;
+ no-sdio;
+ no-sd;
+
+ status = "okay";
+};
diff --git a/arch/arm/dts/shikra-iqs-som.dtsi b/arch/arm/dts/shikra-iqs-som.dtsi
new file mode 100644
index 00000000000..73945bf4211
--- /dev/null
+++ b/arch/arm/dts/shikra-iqs-som.dtsi
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+#include "shikra.dtsi"
+#include "pm8150.dtsi"
+
+/ {
+ gpio-key {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vol_up_n>;
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ wakeup-source;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+};
+
+&pm8150_gpios {
+ vol_up_n: vol-up-n-state {
+ pins = "gpio6";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-pm8150-regulators";
+
+ pm8150_s4: s4 {
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <2040000>;
+ };
+
+ pm8150_s5: s5 {
+ regulator-min-microvolt = <1574000>;
+ regulator-max-microvolt = <2040000>;
+ };
+
+ pm8150_s6: s6 {
+ regulator-min-microvolt = <382000>;
+ regulator-max-microvolt = <1352000>;
+ };
+
+ pm8150_s7: s7 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8150_s8: s8 {
+ regulator-min-microvolt = <570000>;
+ regulator-max-microvolt = <650000>;
+ };
+
+ pm8150_l1: l1 {
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <1304000>;
+ };
+
+ pm8150_l2: l2 {
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8150_l3: l3 {
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <1304000>;
+ };
+
+ pm8150_l4: l4 {
+ regulator-min-microvolt = <875000>;
+ regulator-max-microvolt = <975000>;
+ };
+
+ pm8150_l5: l5 {
+ regulator-min-microvolt = <788000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8150_l6: l6 {
+ regulator-min-microvolt = <875000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ pm8150_l7: l7 {
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ pm8150_l8: l8 {
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1304000>;
+ };
+
+ pm8150_l9: l9 {
+ regulator-min-microvolt = <875000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ pm8150_l10: l10 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ };
+
+ pm8150_l11: l11 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1304000>;
+ };
+
+ pm8150_l12: l12 {
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1950000>;
+ };
+
+ pm8150_l13: l13 {
+ regulator-min-microvolt = <2921000>;
+ regulator-max-microvolt = <3230000>;
+ };
+
+ pm8150_l14: l14 {
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1910000>;
+ };
+
+ pm8150_l15: l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1900000>;
+ };
+
+ pm8150_l16: l16 {
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <3544000>;
+ };
+
+ pm8150_l17: l17 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ };
+
+ pm8150_l18: l18 {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <728000>;
+ };
+ };
+};
diff --git a/arch/arm/dts/shikra.dtsi b/arch/arm/dts/shikra.dtsi
new file mode 100644
index 00000000000..a4334d99c1f
--- /dev/null
+++ b/arch/arm/dts/shikra.dtsi
@@ -0,0 +1,842 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,shikra-gcc.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,rpm-icc.h>
+#include <dt-bindings/interconnect/qcom,shikra.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32764>;
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&l3>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ };
+
+ cpu1: cpu at 100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&l3>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ };
+
+ cpu2: cpu at 200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&l3>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ };
+
+ cpu3: cpu at 300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78c";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&l2_3>;
+ capacity-dmips-mhz = <1946>;
+ dynamic-power-coefficient = <489>;
+
+ l2_3: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3>;
+ cache-size = <0x40000>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ l3: l3-cache {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-unified;
+ cache-size = <0x80000>;
+ };
+ };
+
+ firmware {
+ scm {
+ compatible = "qcom,scm-shikra", "qcom,scm";
+ clocks = <&rpmcc RPM_SMD_CE1_CLK>;
+ clock-names = "core";
+ qcom,dload-mode = <&tcsr_regs 0x13000>;
+ #reset-cells = <1>;
+ interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ };
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0x80000000 0x0 0x0>;
+ };
+
+ pmu-a55 {
+ compatible = "arm,cortex-a55-pmu";
+ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
+ };
+
+ pmu-a78c {
+ compatible = "arm,cortex-a78-pmu";
+ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ rpm: remoteproc {
+ compatible = "qcom,shikra-rpm-proc", "qcom,rpm-proc";
+
+ glink-edge {
+ compatible = "qcom,glink-rpm";
+ interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING 0>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
+
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-shikra", "qcom,glink-smd-rpm";
+ qcom,glink-channels = "rpm_requests";
+
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-shikra", "qcom,rpmcc";
+ clocks = <&xo_board>;
+ clock-names = "xo";
+ #clock-cells = <1>;
+ };
+
+ rpmpd: power-controller {
+ compatible = "qcom,shikra-rpmpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmpd_opp_table>;
+
+ rpmpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmpd_opp_min_svs: opp1 {
+ opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
+ };
+
+ rpmpd_opp_low_svs: opp2 {
+ opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
+ };
+
+ rpmpd_opp_svs: opp3 {
+ opp-level = <RPM_SMD_LEVEL_SVS>;
+ };
+
+ rpmpd_opp_svs_plus: opp4 {
+ opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
+ };
+
+ rpmpd_opp_nom: opp5 {
+ opp-level = <RPM_SMD_LEVEL_NOM>;
+ };
+
+ rpmpd_opp_nom_plus: opp6 {
+ opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
+ };
+
+ rpmpd_opp_turbo: opp7 {
+ opp-level = <RPM_SMD_LEVEL_TURBO>;
+ };
+
+ rpmpd_opp_turbo_plus: opp8 {
+ opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
+ };
+ };
+ };
+ };
+ };
+
+ mpm: interrupt-controller {
+ compatible = "qcom,mpm";
+ qcom,rpm-msg-ram = <&apss_mpm>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING 0>;
+ mboxes = <&apcs_glb 1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #power-domain-cells = <0>;
+ interrupt-parent = <&intc>;
+ qcom,mpm-pin-count = <96>;
+ qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */
+ <12 422>, /* DWC3 ss_phy_irq */
+ <58 272>, /* QUSB2_PHY dmse_hv_vddmx */
+ <59 273>, /* QUSB2_PHY dpse_hv_vddmx */
+ <86 183>, /* MPM wake, SPMI */
+ <90 157>, /* QUSB2_PHY DM */
+ <91 158>; /* QUSB2_PHY DP */
+ };
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: hyp at 80000000 {
+ reg = <0x0 0x80000000 0x0 0x1600000>;
+ no-map;
+ };
+
+ xblboot_mem: xblboot at 85e00000 {
+ reg = <0x0 0x85e00000 0x0 0x100000>;
+ no-map;
+ };
+
+ secdata_apss_mem: secdata-apss at 85fff000 {
+ reg = <0x0 0x85fff000 0x0 0x1000>;
+ no-map;
+ };
+
+ smem_mem: smem at 86000000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x86000000 0x0 0x200000>;
+ no-map;
+
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ audio_heap_mem: audio-heap at 86200000 {
+ reg = <0x0 0x86200000 0x0 0x100000>;
+ no-map;
+ };
+
+ tz_stat_mem: tz-stat at a0000000 {
+ reg = <0x0 0xa0000000 0x0 0x100000>;
+ no-map;
+ };
+
+ qtee_mem: qtee at a1300000 {
+ reg = <0x0 0xa1300000 0x0 0x500000>;
+ no-map;
+ };
+
+ tz_apps_mem: tz-apps at a1800000 {
+ reg = <0x0 0xa1800000 0x0 0x2100000>;
+ no-map;
+ };
+
+ mpss_wlan_mem: mpss-wlan at ab000000 {
+ reg = <0x0 0xab000000 0x0 0x6e00000>;
+ no-map;
+ };
+
+ wlan_mem: wlan at b2300000 {
+ reg = <0x0 0xb2300000 0x0 0x100000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp at b2400000 {
+ reg = <0x0 0xb2400000 0x0 0x1900000>;
+ no-map;
+ };
+
+ gpu_micro_code_mem: gpu-micro-code at b3d00000 {
+ reg = <0x0 0xb3d00000 0x0 0x2000>;
+ no-map;
+ };
+
+ video_mem: video at b3d02000 {
+ reg = <0x0 0xb3d02000 0x0 0x700000>;
+ no-map;
+ };
+
+ lmcu_mem: lmcu at b4402000 {
+ reg = <0x0 0xb4402000 0x0 0x300000>;
+ no-map;
+ };
+
+ lmcu_dtb_mem: lmcu-dtb at b4702000 {
+ reg = <0x0 0xb4702000 0x0 0x40000>;
+ no-map;
+ };
+ };
+
+ soc: soc at 0 {
+ compatible = "simple-bus";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
+ ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
+
+ tcsr_mutex: syscon at 340000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x0 0x00340000 0x0 0x20000>;
+ #hwlock-cells = <1>;
+ };
+
+ tcsr_regs: syscon at 3c0000 {
+ compatible = "qcom,shikra-tcsr", "syscon";
+ reg = <0x0 0x003c0000 0x0 0x40000>;
+ };
+
+ tlmm: pinctrl at 500000 {
+ compatible = "qcom,shikra-tlmm";
+ reg = <0x0 0x00500000 0x0 0x700000>;
+
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ gpio-ranges = <&tlmm 0 0 165>;
+ wakeup-parent = <&mpm>;
+
+ qup_uart0_default: qup-uart0-default-state {
+ pins = "gpio0", "gpio1";
+ function = "qup0_se0";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sdc1_state_on: sdc1-on-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_state_off: sdc1-off-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ drive-strength = <2>;
+ bias-bus-hold;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ drive-strength = <2>;
+ bias-bus-hold;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ drive-strength = <2>;
+ bias-bus-hold;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-bus-hold;
+ };
+ };
+ };
+
+ mem_noc: interconnect at d00000 {
+ compatible = "qcom,shikra-mem-noc-core";
+ reg = <0x0 0x00d00000 0x0 0x43080>;
+ clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>;
+ clock-names = "gpu_axi";
+ #interconnect-cells = <2>;
+ };
+
+ llcc: system-cache-controller at e00000 {
+ compatible = "qcom,shikra-llcc";
+ reg = <0x0 0x00e00000 0x0 0x80000>,
+ <0x0 0x00f00000 0x0 0x80000>,
+ <0x0 0x01000000 0x0 0x80000>;
+ reg-names = "llcc0_base",
+ "llcc1_base",
+ "llcc_broadcast_base";
+ interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ gcc: clock-controller at 1400000 {
+ compatible = "qcom,shikra-gcc";
+ reg = <0x0 0x01400000 0x0 0x1f0000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ system_noc: interconnect at 1880000 {
+ compatible = "qcom,shikra-sys-noc";
+ reg = <0x0 0x01880000 0x0 0x6a080>;
+ clocks = <&gcc GCC_EMAC0_AXI_SYS_NOC_CLK>,
+ <&gcc GCC_EMAC1_AXI_SYS_NOC_CLK>,
+ <&gcc GCC_SYS_NOC_USB2_PRIM_AXI_CLK>,
+ <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>;
+ clock-names = "emac0_axi",
+ "emac1_axi",
+ "usb2_axi",
+ "usb3_axi";
+ #interconnect-cells = <2>;
+
+ clk_virt: interconnect-clk {
+ compatible = "qcom,shikra-clk-virt";
+ #interconnect-cells = <2>;
+ };
+
+ mc_virt: interconnect-mc {
+ compatible = "qcom,shikra-mc-virt";
+ #interconnect-cells = <2>;
+ };
+
+ mmrt_virt: interconnect-mmrt {
+ compatible = "qcom,shikra-mmrt-virt";
+ #interconnect-cells = <2>;
+ };
+
+ mmnrt_virt: interconnect-mmnrt {
+ compatible = "qcom,shikra-mmnrt-virt";
+ #interconnect-cells = <2>;
+ };
+ };
+
+ config_noc: interconnect at 1900000 {
+ compatible = "qcom,shikra-config-noc";
+ reg = <0x0 0x01900000 0x0 0x8080>;
+ #interconnect-cells = <2>;
+ };
+
+ qfprom: efuse at 1b44000 {
+ compatible = "qcom,shikra-qfprom", "qcom,qfprom";
+ reg = <0x0 0x01b44000 0x0 0x3000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qusb2_hstx_trim_1: hstx-trim at 25b {
+ reg = <0x25b 0x1>;
+ bits = <1 4>;
+ };
+
+ gpu_speed_bin: gpu-speed-bin at 2006 {
+ reg = <0x2006 0x2>;
+ bits = <5 8>;
+ };
+ };
+
+ spmi_bus: spmi at 1c40000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x0 0x01c40000 0x0 0x1100>,
+ <0x0 0x01e00000 0x0 0x2000000>,
+ <0x0 0x03e00000 0x0 0x100000>,
+ <0x0 0x03f00000 0x0 0xa0000>,
+ <0x0 0x01c0a000 0x0 0x26000>;
+ reg-names = "core",
+ "chnls",
+ "obsrvr",
+ "intr",
+ "cnfg";
+ interrupts-extended = <&mpm 86 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "periph_irq";
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ qcom,channel = <0>;
+ qcom,ee = <0>;
+ };
+
+ rpm_msg_ram: sram at 45f0000 {
+ compatible = "qcom,rpm-msg-ram", "mmio-sram";
+ reg = <0x0 0x045f0000 0x0 0x7000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x045f0000 0x7000>;
+
+ apss_mpm: sram at 1b8 {
+ reg = <0x1b8 0x48>;
+ };
+ };
+
+ sram at 4690000 {
+ compatible = "qcom,rpm-stats";
+ reg = <0x0 0x04690000 0x0 0x14000>;
+ };
+
+ sdhc_1: mmc at 4744000 {
+ compatible = "qcom,shikra-sdhci", "qcom,sdhci-msm-v5";
+
+ reg = <0x0 0x04744000 0x0 0x1000>,
+ <0x0 0x04745000 0x0 0x1000>;
+ reg-names = "hc",
+ "cqhci";
+
+ iommus = <&apps_smmu 0xc0 0x0>;
+
+ interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "hc_irq",
+ "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface",
+ "core",
+ "xo";
+
+ interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &config_noc SLAVE_SDCC_1 RPM_ACTIVE_TAG>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+
+ power-domains = <&rpmpd RPMPD_VDDCX>;
+ operating-points-v2 = <&sdhc1_opp_table>;
+
+ qcom,dll-config = <0x000f642c>;
+ qcom,ddr-config = <0x80040868>;
+
+ bus-width = <8>;
+
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+
+ resets = <&gcc GCC_SDCC1_BCR>;
+
+ status = "disabled";
+
+ sdhc1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ opp-peak-kBps = <250000 133320>;
+ opp-avg-kBps = <104000 0>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ opp-peak-kBps = <800000 300000>;
+ opp-avg-kBps = <400000 0>;
+ };
+ };
+ };
+
+ qupv3_0: geniqup at 4ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x04ac0000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ uart0: serial at 4a80000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x04a80000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart0_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+ };
+
+ sram at c11e000 {
+ compatible = "qcom,shikra-imem", "mmio-sram";
+ reg = <0x0 0x0c11e000 0x0 0x1000>;
+ ranges = <0x0 0x0 0x0c11e000 0x1000>;
+
+ no-memory-wc;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pil-sram at 94c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x94c 0xc8>;
+ };
+ };
+
+ apps_smmu: iommu at c600000 {
+ compatible = "qcom,shikra-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x0c600000 0x0 0x80000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ intc: interrupt-controller at f200000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0xf200000 0x0 0x10000>,
+ <0x0 0xf240000 0x0 0x80000>;
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ #interrupt-cells = <4>;
+ interrupt-controller;
+
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x20000>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2>;
+ };
+
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu3>;
+ };
+ };
+ };
+
+ apcs_glb: mailbox at f400000 {
+ compatible = "qcom,shikra-apss-shared", "qcom,sdm845-apss-shared";
+ reg = <0x0 0x0f400000 0x0 0x1000>;
+ #mbox-cells = <1>;
+ };
+
+ watchdog at f410000 {
+ compatible = "qcom,apss-wdt-shikra", "qcom,kpss-wdt";
+ reg = <0x0 0x0f410000 0x0 0x1000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&sleep_clk>;
+ };
+
+ timer at f420000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0 0x0f420000 0x0 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x10000000>;
+
+ frame at f421000 {
+ reg = <0x0f421000 0x1000>,
+ <0x0f422000 0x1000>;
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ frame at f423000 {
+ reg = <0x0f423000 0x1000>;
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+
+ frame at f425000 {
+ reg = <0x0f425000 0x1000>;
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+
+ frame at f427000 {
+ reg = <0x0f427000 0x1000>;
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+
+ frame at f429000 {
+ reg = <0x0f429000 0x1000>;
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+
+ frame at f42b000 {
+ reg = <0x0f42b000 0x1000>;
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+
+ frame at f42d000 {
+ reg = <0x0f42d000 0x1000>;
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+
+ interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW 0>;
+ };
+};
diff --git a/include/dt-bindings/clock/qcom,shikra-gcc.h b/include/dt-bindings/clock/qcom,shikra-gcc.h
new file mode 100644
index 00000000000..dc55e5652ca
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,shikra-gcc.h
@@ -0,0 +1,262 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SHIKRA_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_SHIKRA_H
+
+/* GCC clocks */
+#define GPLL0 0
+#define GPLL0_OUT_AUX2 1
+#define GPLL1 2
+#define GPLL10 3
+#define GPLL11 4
+#define GPLL12 5
+#define GPLL12_OUT_AUX2 6
+#define GPLL3 7
+#define GPLL3_OUT_MAIN 8
+#define GPLL4 9
+#define GPLL5 10
+#define GPLL6 11
+#define GPLL6_OUT_MAIN 12
+#define GPLL7 13
+#define GPLL8 14
+#define GPLL8_OUT_MAIN 15
+#define GPLL9 16
+#define GPLL9_OUT_MAIN 17
+#define GCC_AHB2PHY_CSI_CLK 18
+#define GCC_AHB2PHY_USB_CLK 19
+#define GCC_BOOT_ROM_AHB_CLK 20
+#define GCC_CAM_THROTTLE_NRT_CLK 21
+#define GCC_CAM_THROTTLE_RT_CLK 22
+#define GCC_CAMERA_AHB_CLK 23
+#define GCC_CAMERA_XO_CLK 24
+#define GCC_CAMSS_AXI_CLK 25
+#define GCC_CAMSS_AXI_CLK_SRC 26
+#define GCC_CAMSS_CAMNOC_ATB_CLK 27
+#define GCC_CAMSS_CAMNOC_DRAGONLINK_ATB_CLK 28
+#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 29
+#define GCC_CAMSS_CCI_0_CLK 30
+#define GCC_CAMSS_CCI_CLK_SRC 31
+#define GCC_CAMSS_CPHY_0_CLK 32
+#define GCC_CAMSS_CPHY_1_CLK 33
+#define GCC_CAMSS_CSI0PHYTIMER_CLK 34
+#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 35
+#define GCC_CAMSS_CSI1PHYTIMER_CLK 36
+#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 37
+#define GCC_CAMSS_MCLK0_CLK 38
+#define GCC_CAMSS_MCLK0_CLK_SRC 39
+#define GCC_CAMSS_MCLK1_CLK 40
+#define GCC_CAMSS_MCLK1_CLK_SRC 41
+#define GCC_CAMSS_MCLK2_CLK 42
+#define GCC_CAMSS_MCLK2_CLK_SRC 43
+#define GCC_CAMSS_MCLK3_CLK 44
+#define GCC_CAMSS_MCLK3_CLK_SRC 45
+#define GCC_CAMSS_NRT_AXI_CLK 46
+#define GCC_CAMSS_OPE_AHB_CLK 47
+#define GCC_CAMSS_OPE_AHB_CLK_SRC 48
+#define GCC_CAMSS_OPE_CLK 49
+#define GCC_CAMSS_OPE_CLK_SRC 50
+#define GCC_CAMSS_RT_AXI_CLK 51
+#define GCC_CAMSS_TFE_0_CLK 52
+#define GCC_CAMSS_TFE_0_CLK_SRC 53
+#define GCC_CAMSS_TFE_0_CPHY_RX_CLK 54
+#define GCC_CAMSS_TFE_0_CSID_CLK 55
+#define GCC_CAMSS_TFE_0_CSID_CLK_SRC 56
+#define GCC_CAMSS_TFE_1_CLK 57
+#define GCC_CAMSS_TFE_1_CLK_SRC 58
+#define GCC_CAMSS_TFE_1_CPHY_RX_CLK 59
+#define GCC_CAMSS_TFE_1_CSID_CLK 60
+#define GCC_CAMSS_TFE_1_CSID_CLK_SRC 61
+#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC 62
+#define GCC_CAMSS_TOP_AHB_CLK 63
+#define GCC_CAMSS_TOP_AHB_CLK_SRC 64
+#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 65
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 66
+#define GCC_DDRSS_GPU_AXI_CLK 67
+#define GCC_DDRSS_MEMNOC_PCIE_SF_CLK 68
+#define GCC_DISP_AHB_CLK 69
+#define GCC_DISP_GPLL0_CLK_SRC 70
+#define GCC_DISP_GPLL0_DIV_CLK_SRC 71
+#define GCC_DISP_HF_AXI_CLK 72
+#define GCC_DISP_THROTTLE_CORE_CLK 73
+#define GCC_DISP_XO_CLK 74
+#define GCC_EMAC0_AHB_CLK 75
+#define GCC_EMAC0_AXI_CLK 76
+#define GCC_EMAC0_AXI_CLK_SRC 77
+#define GCC_EMAC0_AXI_SYS_NOC_CLK 78
+#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK 79
+#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC 80
+#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK 81
+#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC 82
+#define GCC_EMAC0_PHY_AUX_CLK 83
+#define GCC_EMAC0_PHY_AUX_CLK_SRC 84
+#define GCC_EMAC0_PTP_CLK 85
+#define GCC_EMAC0_PTP_CLK_SRC 86
+#define GCC_EMAC0_RGMII_CLK 87
+#define GCC_EMAC0_RGMII_CLK_SRC 88
+#define GCC_EMAC1_AHB_CLK 89
+#define GCC_EMAC1_AXI_CLK 90
+#define GCC_EMAC1_AXI_CLK_SRC 91
+#define GCC_EMAC1_AXI_SYS_NOC_CLK 92
+#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK 93
+#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC 94
+#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK 95
+#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC 96
+#define GCC_EMAC1_PHY_AUX_CLK 97
+#define GCC_EMAC1_PHY_AUX_CLK_SRC 98
+#define GCC_EMAC1_PTP_CLK 99
+#define GCC_EMAC1_PTP_CLK_SRC 100
+#define GCC_EMAC1_RGMII_CLK 101
+#define GCC_EMAC1_RGMII_CLK_SRC 102
+#define GCC_GP1_CLK 103
+#define GCC_GP1_CLK_SRC 104
+#define GCC_GP2_CLK 105
+#define GCC_GP2_CLK_SRC 106
+#define GCC_GP3_CLK 107
+#define GCC_GP3_CLK_SRC 108
+#define GCC_GPU_CFG_AHB_CLK 109
+#define GCC_GPU_GPLL0_CLK_SRC 110
+#define GCC_GPU_GPLL0_DIV_CLK_SRC 111
+#define GCC_GPU_IREF_CLK 112
+#define GCC_GPU_MEMNOC_GFX_CLK 113
+#define GCC_GPU_SMMU_VOTE_CLK 114
+#define GCC_GPU_SNOC_DVM_GFX_CLK 115
+#define GCC_GPU_THROTTLE_CORE_CLK 116
+#define GCC_LPASS_CONFIG_CLK 117
+#define GCC_LPASS_CORE_AXIM_CLK 118
+#define GCC_MMU_TCU_VOTE_CLK 119
+#define GCC_PCIE_AUX_CLK 120
+#define GCC_PCIE_AUX_CLK_SRC 121
+#define GCC_PCIE_AUX_PHY_CLK_SRC 122
+#define GCC_PCIE_CFG_AHB_CLK 123
+#define GCC_PCIE_CLKREF_EN 124
+#define GCC_PCIE_MSTR_AXI_CLK 125
+#define GCC_PCIE_PIPE_CLK 126
+#define GCC_PCIE_PIPE_CLK_SRC 127
+#define GCC_PCIE_RCHNG_PHY_CLK 128
+#define GCC_PCIE_RCHNG_PHY_CLK_SRC 129
+#define GCC_PCIE_SLEEP_CLK 130
+#define GCC_PCIE_SLV_AXI_CLK 131
+#define GCC_PCIE_SLV_Q2A_AXI_CLK 132
+#define GCC_PCIE_TBU_CLK 133
+#define GCC_PCIE_THROTTLE_CORE_CLK 134
+#define GCC_PCIE_THROTTLE_XO_CLK 135
+#define GCC_PCIE_TILE_AXI_SYS_NOC_CLK 136
+#define GCC_PDM2_CLK 137
+#define GCC_PDM2_CLK_SRC 138
+#define GCC_PDM_AHB_CLK 139
+#define GCC_PDM_XO4_CLK 140
+#define GCC_PWM0_XO512_CLK 141
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK 142
+#define GCC_QMIP_CAMERA_RT_AHB_CLK 143
+#define GCC_QMIP_DISP_AHB_CLK 144
+#define GCC_QMIP_GPU_CFG_AHB_CLK 145
+#define GCC_QMIP_PCIE_CFG_AHB_CLK 146
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 147
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK 148
+#define GCC_QUPV3_WRAP0_CORE_CLK 149
+#define GCC_QUPV3_WRAP0_S0_CLK 150
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC 151
+#define GCC_QUPV3_WRAP0_S1_CLK 152
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC 153
+#define GCC_QUPV3_WRAP0_S2_CLK 154
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC 155
+#define GCC_QUPV3_WRAP0_S3_CLK 156
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC 157
+#define GCC_QUPV3_WRAP0_S4_CLK 158
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC 159
+#define GCC_QUPV3_WRAP0_S5_CLK 160
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC 161
+#define GCC_QUPV3_WRAP0_S6_CLK 162
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC 163
+#define GCC_QUPV3_WRAP0_S7_CLK 164
+#define GCC_QUPV3_WRAP0_S7_CLK_SRC 165
+#define GCC_QUPV3_WRAP0_S8_CLK 166
+#define GCC_QUPV3_WRAP0_S8_CLK_SRC 167
+#define GCC_QUPV3_WRAP0_S9_CLK 168
+#define GCC_QUPV3_WRAP0_S9_CLK_SRC 169
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK 170
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK 171
+#define GCC_SDCC1_AHB_CLK 172
+#define GCC_SDCC1_APPS_CLK 173
+#define GCC_SDCC1_APPS_CLK_SRC 174
+#define GCC_SDCC1_ICE_CORE_CLK 175
+#define GCC_SDCC1_ICE_CORE_CLK_SRC 176
+#define GCC_SDCC2_AHB_CLK 177
+#define GCC_SDCC2_APPS_CLK 178
+#define GCC_SDCC2_APPS_CLK_SRC 179
+#define GCC_SYS_NOC_CPUSS_AHB_CLK 180
+#define GCC_SYS_NOC_USB2_PRIM_AXI_CLK 181
+#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 182
+#define GCC_TSCSS_AHB_CLK 183
+#define GCC_TSCSS_CLK_SRC 184
+#define GCC_TSCSS_CNTR_CLK 185
+#define GCC_TSCSS_ETU_CLK 186
+#define GCC_UFS_CLKREF_EN 187
+#define GCC_USB20_MASTER_CLK 188
+#define GCC_USB20_MASTER_CLK_SRC 189
+#define GCC_USB20_MOCK_UTMI_CLK 190
+#define GCC_USB20_MOCK_UTMI_CLK_SRC 191
+#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 192
+#define GCC_USB20_SLEEP_CLK 193
+#define GCC_USB30_PRIM_MASTER_CLK 194
+#define GCC_USB30_PRIM_MASTER_CLK_SRC 195
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK 196
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 197
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 198
+#define GCC_USB30_PRIM_SLEEP_CLK 199
+#define GCC_USB3_PRIM_CLKREF_EN 200
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 201
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 202
+#define GCC_USB3_PRIM_PHY_PIPE_CLK 203
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 204
+#define GCC_VCODEC0_AXI_CLK 205
+#define GCC_VENUS_AHB_CLK 206
+#define GCC_VENUS_CTL_AXI_CLK 207
+#define GCC_VIDEO_AHB_CLK 208
+#define GCC_VIDEO_AXI0_CLK 209
+#define GCC_VIDEO_THROTTLE_CORE_CLK 210
+#define GCC_VIDEO_VCODEC0_SYS_CLK 211
+#define GCC_VIDEO_VENUS_CLK_SRC 212
+#define GCC_VIDEO_VENUS_CTL_CLK 213
+#define GCC_VIDEO_XO_CLK 214
+
+/* GCC power domains */
+#define GCC_CAMSS_TOP_GDSC 0
+#define GCC_EMAC0_GDSC 1
+#define GCC_EMAC1_GDSC 2
+#define GCC_PCIE_GDSC 3
+#define GCC_USB20_GDSC 4
+#define GCC_USB30_PRIM_GDSC 5
+#define GCC_VCODEC0_GDSC 6
+#define GCC_VENUS_GDSC 7
+
+/* GCC resets */
+#define GCC_CAMSS_OPE_BCR 0
+#define GCC_CAMSS_TFE_BCR 1
+#define GCC_CAMSS_TOP_BCR 2
+#define GCC_EMAC0_BCR 3
+#define GCC_EMAC1_BCR 4
+#define GCC_GPU_BCR 5
+#define GCC_MMSS_BCR 6
+#define GCC_PCIE_BCR 7
+#define GCC_PCIE_PHY_BCR 8
+#define GCC_PDM_BCR 9
+#define GCC_QUPV3_WRAPPER_0_BCR 10
+#define GCC_QUSB2PHY_PRIM_BCR 11
+#define GCC_QUSB2PHY_SEC_BCR 12
+#define GCC_SDCC1_BCR 13
+#define GCC_SDCC2_BCR 14
+#define GCC_TSCSS_BCR 15
+#define GCC_USB20_BCR 16
+#define GCC_USB30_PRIM_BCR 17
+#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 18
+#define GCC_USB3_PHY_PRIM_SP0_BCR 19
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 20
+#define GCC_VCODEC0_BCR 21
+#define GCC_VENUS_BCR 22
+#define GCC_VIDEO_INTERFACE_BCR 23
+
+#endif
diff --git a/include/dt-bindings/interconnect/qcom,shikra.h b/include/dt-bindings/interconnect/qcom,shikra.h
new file mode 100644
index 00000000000..a42ea22ee16
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,shikra.h
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SHIKRA_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_SHIKRA_H
+
+#define MASTER_QUP_CORE_0 0
+#define SLAVE_QUP_CORE_0 1
+
+#define SNOC_CNOC_MAS 0
+#define MASTER_QDSS_DAP 1
+#define SLAVE_AHB2PHY_USB 2
+#define SLAVE_APSS_THROTTLE_CFG 3
+#define SLAVE_AUDIO 4
+#define SLAVE_BOOT_ROM 5
+#define SLAVE_CAMERA_NRT_THROTTLE_CFG 6
+#define SLAVE_CAMERA_CFG 7
+#define SLAVE_CDSP_THROTTLE_CFG 8
+#define SLAVE_CLK_CTL 9
+#define SLAVE_DSP_CFG 10
+#define SLAVE_RBCPR_CX_CFG 11
+#define SLAVE_RBCPR_MX_CFG 12
+#define SLAVE_CRYPTO_0_CFG 13
+#define SLAVE_DDR_SS_CFG 14
+#define SLAVE_DISPLAY_CFG 15
+#define SLAVE_EMAC0_CFG 16
+#define SLAVE_EMAC1_CFG 17
+#define SLAVE_GPU_CFG 18
+#define SLAVE_GPU_THROTTLE_CFG 19
+#define SLAVE_HWKM 20
+#define SLAVE_IMEM_CFG 21
+#define SLAVE_MAPSS 22
+#define SLAVE_MDSP_MPU_CFG 23
+#define SLAVE_MESSAGE_RAM 24
+#define SLAVE_MSS 25
+#define SLAVE_PCIE_CFG 26
+#define SLAVE_PDM 27
+#define SLAVE_PIMEM_CFG 28
+#define SLAVE_PKA_WRAPPER_CFG 29
+#define SLAVE_PMIC_ARB 30
+#define SLAVE_QDSS_CFG 31
+#define SLAVE_QM_CFG 32
+#define SLAVE_QM_MPU_CFG 33
+#define SLAVE_QPIC 34
+#define SLAVE_QUP_0 35
+#define SLAVE_RPM 36
+#define SLAVE_SDCC_1 37
+#define SLAVE_SDCC_2 38
+#define SLAVE_SECURITY 39
+#define SLAVE_SNOC_CFG 40
+#define SNOC_SF_THROTTLE_CFG 41
+#define SLAVE_TLMM 42
+#define SLAVE_TSCSS 43
+#define SLAVE_USB2 44
+#define SLAVE_USB3 45
+#define SLAVE_VENUS_CFG 46
+#define SLAVE_VENUS_THROTTLE_CFG 47
+#define SLAVE_VSENSE_CTRL_CFG 48
+#define SLAVE_SERVICE_CNOC 49
+
+#define MASTER_LLCC 0
+#define SLAVE_EBI_CH0 1
+
+#define MASTER_GRAPHICS_3D 0
+#define MASTER_MNOC_HF_MEM_NOC 1
+#define MASTER_ANOC_PCIE_MEM_NOC 2
+#define MASTER_SNOC_SF_MEM_NOC 3
+#define MASTER_AMPSS_M0 4
+#define MASTER_SYS_TCU 5
+#define SLAVE_LLCC 6
+#define SLAVE_MEMNOC_SNOC 7
+#define SLAVE_MEM_NOC_PCIE_SNOC 8
+
+#define MASTER_CAMNOC_SF 0
+#define MASTER_VIDEO_P0 1
+#define MASTER_VIDEO_PROC 2
+#define SLAVE_MMNRT_VIRT 3
+
+#define MASTER_CAMNOC_HF 0
+#define MASTER_MDP_PORT0 1
+#define MASTER_MMRT_VIRT 2
+#define SLAVE_MM_MEMNOC 3
+
+#define MASTER_SNOC_CFG 0
+#define MASTER_TIC 1
+#define MASTER_ANOC_SNOC 2
+#define MASTER_MEMNOC_PCIE 3
+#define MASTER_MEMNOC_SNOC 4
+#define MASTER_PIMEM 5
+#define MASTER_PCIE2_0 6
+#define MASTER_QDSS_BAM 7
+#define MASTER_QPIC 8
+#define MASTER_QUP_0 9
+#define CNOC_SNOC_MAS 10
+#define MASTER_AUDIO 11
+#define MASTER_EMAC_0 12
+#define MASTER_EMAC_1 13
+#define MASTER_QDSS_ETR 14
+#define MASTER_SDCC_1 15
+#define MASTER_SDCC_2 16
+#define MASTER_USB2_0 17
+#define MASTER_USB3 18
+#define MASTER_CRYPTO_CORE0 19
+#define SLAVE_APPSS 20
+#define SLAVE_MCUSS 21
+#define SLAVE_WCSS 22
+#define SLAVE_MEMNOC_SF 23
+#define SNOC_CNOC_SLV 24
+#define SLAVE_BOOTIMEM 25
+#define SLAVE_OCIMEM 26
+#define SLAVE_PIMEM 27
+#define SLAVE_SERVICE_SNOC 28
+#define SLAVE_PCIE2_0 29
+#define SLAVE_QDSS_STM 30
+#define SLAVE_TCU 31
+#define SLAVE_PCIE_MEMNOC 32
+#define SLAVE_ANOC_SNOC 33
+
+#endif
--
2.34.1
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