[PATCH 1/2] rockchip: rk3568: make the WDT trigger a first global reset

Andreas Zdziarstek andreas.zdziarstek at gmail.com
Sat Jun 20 00:08:19 CEST 2026


Default is a second global reset which causes a system hang on a timeout
in U-Boot.

Verified on the Hardkernel ODROID-M1S (RK3566): a watchdog timeout now
cleanly reboots the board.

Signed-off-by: Andreas Zdziarstek <andreas.zdziarstek at gmail.com>
---
 arch/arm/mach-rockchip/rk3568/rk3568.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
index 2b1eafee37c..77610a6a6ec 100644
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -37,6 +37,10 @@
 #define CPU_GRF_BASE		0xfdc30000
 #define GRF_CORE_PVTPLL_CON0	(0x10)
 
+#define CRU_BASE		0xfdd20000
+#define CRU_GLB_RST_CON		(CRU_BASE + 0x0dc)
+#define WDT_GLB_SRST_CTRL	BIT(1)
+
 /* PMU_GRF_GPIO0D_IOMUX_L */
 enum {
 	GPIO0D1_SHIFT		= 4,
@@ -146,6 +150,10 @@ int arch_cpu_init(void)
 	writel((PMU_PD_VO_DWN_ENA << 16),
 	       PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON);
 #endif
+
+	/* Make WDT trigger a first global reset */
+	setbits_le32((void __iomem *)CRU_GLB_RST_CON, WDT_GLB_SRST_CTRL);
+
 	return 0;
 }
 
-- 
2.53.0



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