[PATCH 0/2] rockchip: odroid-m1s/rk3566 watchdog support
Quentin Schulz
quentin.schulz at cherry.de
Tue Jun 23 11:10:39 CEST 2026
Hi Andreas,
On 6/20/26 12:08 AM, Andreas Zdziarstek wrote:
> [You don't often get email from andreas.zdziarstek at gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> I experimented with the Synopsys DesignWare watchdog on an Odroid-M1S
> (RK3566). On current master, the watchdog is present in device-tree.
> After activating the relevant options in .config, U-Boot tried probing
> it but failed, aborting at a failing clk_enable(). Current next branch
> already has a patch for that in the driver (d62801d09441) and with that
> wdt query and servicing works.
>
> However, a timeout or wdt expire causes a hung SoC. There are two
> possible "global resets" the watchdog may trigger, set in the CRU
> registers, as per the TRM. Default is the "second" reset.
>
> Unfortunately, the TRM is rather tight-lipped about what each one really
> does. Per experimentation: Setting it to the "first" global reset fixes
As per TRM (2.8.4 Global Software Reset):
"""
glb_srstn_1 resets almost all logic except some registers just
supporting hardware reset.
glb_srstn_2 resets almost all logic except GRFs and GPIOs.
"""
which is similarly worded in PX30 TRM for example.
> the hang and makes the watchdog work as expected in U-Boot. This is the
> first patch. As the PX30 does the same thing in its arch_cpu_init(), I
> believe this to be the way to go but I am curious to hear if anybody has
> more technical insight on this.
>
I'm not sure there's much more we can know (would debugging this with
JTAG help? I've never used it so don't know). But it's been a pain point
on various Rockchip SoCs already, I'm quite surprised the default is
still global reset 1 and not global reset 2.
Cheers,
Quentin
More information about the U-Boot
mailing list