[PATCH] soc: xilinx: zynqmp: Add TCG variant detection for ZU3TCG

[Padmarao Begari]

The XCZU3TCG device shares IDCODE 0x04718093 with XCZU3TEG but has
the GPU disable eFuse bit set (Consumer Grade, no GPU). Previously,
the TEG detection branch appended "teg" unconditionally, causing
U-Boot to report the device as zu3teg and failing bitstream ID
checks for xczu3tcg bitstreams.

Check EFUSE_GPU_DIS_MASK in the TEG branch to distinguish the two
sub-variants, mirroring the existing EG/CG detection logic:
- GPU disabled -> TCG family -> "zu3tcg"
- GPU enabled  -> TEG family -> "zu3teg"

Fixes: fa2f0c97af96 ("soc: zynqmp: Add the IDcode for TEG variant")
Signed-off-by: Padmarao Begari <padmarao.begari at amd.com>
---
 drivers/soc/soc_xilinx_zynqmp.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c
index 4abc73013eb..0e13e230914 100644
--- a/drivers/soc/soc_xilinx_zynqmp.c
+++ b/drivers/soc/soc_xilinx_zynqmp.c
@@ -358,7 +358,9 @@ static int soc_xilinx_zynqmp_detect_machine(struct udevice *dev, u32 idcode,
 	} else if (device->variants & ZYNQMP_VARIANT_DR_SE) {
 		strlcat(priv->machine, "dr_SE", sizeof(priv->machine));
 	} else if (device->variants & ZYNQMP_VARIANT_TEG) {
-		strlcat(priv->machine, "teg", sizeof(priv->machine));
+		/* Devices with TEG variant might be TEG or TCG family */
+		strlcat(priv->machine, (idcode2 & EFUSE_GPU_DIS_MASK) ?
+			"tcg" : "teg", sizeof(priv->machine));
 	}
 
 	return 0;
-- 
2.34.1