[PATCH] Board phycore_imx8mm: spl: add 1 and 4GB RAM timings

[Teresa Remmet]

Hello INgo,

Am Dienstag, dem 23.06.2026 um 08:24 +0200 schrieb INgo Rah:
> The Phytec Tauri L is sold with other memory configurations then 2
> GB.
> Gather the memory size from the EEPROM of the underlaying PhyCore
> module
> and set timing information accordingly.
> 
> Signed-off-by: INgo Rah <ingo.rah at linutronix.de>
> Reviewed-by: Benedikt Spranger <b.spranger at linutronix.de>
> Reviewed-by: Gregor Herburger <gregor.herburger at linutronix.de>
> ---
> Board phycore_imx8mm: spl: add 1 and 4GB RAM timings
>   This patch heavily borrowed code from git://git.phytec.de/u-boot-
> imx commit
>   00ac765d6032 ("BSPIMX8M-2893 board: phycore_imx8mm: spl: add 1 and
> 4GB RAM
>   timings") and commit 93962421d7b4 ("BSPIMX8M-2893 board:
> phycore_imx8mm:
>   spl: add 1 and 4GB RAM timings")

there has been meanwhile an new update of the RAM Timings.
Can you checkout downstream commits:
f5e9c4e8cb74 ("board: phytec: phycore-imx8mm: Update RAM Timings")
a2aeeb82e1d9 ("BSPIMX8M-3891: board: phytec: phycore-imx8mm: Set
correct RAM timing fallback")

> 
>  .../dts/imx8mm-phygate-tauri-l-u-boot.dtsi    |  8 ++++++
>  board/phytec/common/imx8m_som_detection.h     |  7 ++++++
>  board/phytec/phycore_imx8mm/lpddr4_timing.c   | 25
> +++++++++++++++++++
>  board/phytec/phycore_imx8mm/lpddr4_timing.h   | 12 +++++++++
>  board/phytec/phycore_imx8mm/spl.c             | 24
> +++++++++++++++++-
>  configs/imx8mm-phygate-tauri-l_defconfig      |  1 +
>  6 files changed, 76 insertions(+), 1 deletion(-)
>  create mode 100644 board/phytec/phycore_imx8mm/lpddr4_timing.h
> 

[...]

> +#endif /* __LPDDR4_TIMING_H__ */
> diff --git a/board/phytec/phycore_imx8mm/spl.c
> b/board/phytec/phycore_imx8mm/spl.c
> index e688793bc74..c9f2243c819 100644
> --- a/board/phytec/phycore_imx8mm/spl.c
> +++ b/board/phytec/phycore_imx8mm/spl.c
> @@ -16,6 +16,7 @@
>  #include <log.h>
>  #include <spl.h>
>  
> +#include "lpddr4_timing.h"
>  #include "../common/imx8m_som_detection.h"
>  
>  #define EEPROM_ADDR		0x51
> @@ -42,6 +43,7 @@ int spl_board_boot_device(enum boot_device
> boot_dev_spl)
>  static void spl_dram_init(void)
>  {
>  	int ret;
> +	enum phytec_imx8mm_ddr_eeprom_code size =
> PHYTEC_EEPROM_INVAL;
>  
>  	ret = phytec_eeprom_data_setup_fallback(NULL, 0,
> EEPROM_ADDR,
>  			EEPROM_ADDR_FALLBACK);
> @@ -49,10 +51,30 @@ static void spl_dram_init(void)
>  		goto out;
>  
>  	ret = phytec_imx8m_detect(NULL);
> -	if (!ret)
> +	if (!ret) {
>  		phytec_print_som_info(NULL);
> +		size = phytec_get_imx8m_ddr_size(NULL);
> +	}
>  
> +	switch (size) {
> +	case PHYTEC_IMX8MM_DDR_1GB:
> +		puts("1 GiB\n");

I would prefer if you drop the output here and below 
as u-boot proper prints the size, too.

Teresa

> +		set_dram_timings_1gb();
> +		break;
> +	case PHYTEC_IMX8MM_DDR_2GB:
> +		puts("2 GiB\n");
> +		break;
> +	case PHYTEC_IMX8MM_DDR_4GB:
> +		puts("4 GiB\n");
> +		set_dram_timings_4gb();
> +		break;
> +	default:
> +		goto out;
> +	}
> +	ddr_init(&dram_timing);
> +	return;
>  out:
> +	puts("Could not detect correct RAM size. Fall back to
> default.\n");
>  	ddr_init(&dram_timing);
>  }
>  
> diff --git a/configs/imx8mm-phygate-tauri-l_defconfig
> b/configs/imx8mm-phygate-tauri-l_defconfig
> index e34f12cabf3..866e5d1dbb3 100644
> --- a/configs/imx8mm-phygate-tauri-l_defconfig
> +++ b/configs/imx8mm-phygate-tauri-l_defconfig
> @@ -4,6 +4,7 @@ CONFIG_TEXT_BASE=0x40200000
>  CONFIG_SYS_MALLOC_LEN=0x2000000
>  CONFIG_SPL_GPIO=y
>  CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_PHYTEC_SOM_DETECTION=y
>  CONFIG_ENV_SIZE=0x10000
>  CONFIG_ENV_OFFSET=0x3C0000
>  CONFIG_DM_GPIO=y
> ---
> base-commit: f072620dc9ffda00b010783da27c41231c3a439b
> branch: feature/phygate
> 

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