[PATCH] mtd: spi-nor: Add GigaDevice GD25LQ16 support
Takahiro.Kuwano at infineon.com
Takahiro.Kuwano at infineon.com
Wed Jun 24 10:37:30 CEST 2026
Hello Marek,
>
> On 6/12/26 11:51 AM, Takahiro.Kuwano at infineon.com wrote:
>
> Hello Kuwano-san,
>
> +CC GigaDevice
>
> >> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> >> index c0fa98424aa..d3a24b51daf 100644
> >> --- a/drivers/mtd/spi/spi-nor-ids.c
> >> +++ b/drivers/mtd/spi/spi-nor-ids.c
> >> @@ -117,6 +117,11 @@ const struct flash_info spi_nor_ids[] = {
> >> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> >> SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> >> },
> >> + {
> >> + INFO("gd25lq16", 0xc86015, 0, 64 * 1024, 32,
> >> + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> >> + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> >
> > I could find a datasheet of GD25LQ16E that mentions the same ID (C8 60 15).
> > https://www.mouser.com/datasheet/2/870/gd25lq16e_datasheet_v1_2_20210108-
> 2399660.pdf?srsltid=AfmBOopEr50lYWZuINw4geNljXqWZxHqvrYc-_HyJi7ISbOc_9RRaiC1
> >
> > This chip has 4 BP bits (BP3..BP0) + TB (BP4).
> > The u-boot driver doesn't support 4-bit BP yet so locking feature shouldn't
> > work as expected.
>
> That is a good point.
>
> I had a brief look at it, and it looks like it would be possible to pick
> a couple of kernel patches to support the various SR topologies, I
> created a test branch [1] with those patches. Do you think this is a
> workable approach ?
>
Yes, I think it's definitely workable. Good to know we already have a set of
working patches. At the same time, we should split the protection logics from
core like Linux (i.e., mtd/spi-nor/swp.c). Is this also something you can
assist with?
In a series [2], I split ID tables and SFDP, but not for protection.
> [1]
> https://source.denx.de/u-boot/custodians/u-boot-usb/-/commits/spi-nor-4bit-sr
>
> --
> Best regards,
> Marek Vasut
Thanks!
Takahiro
[2]
https://lore.kernel.org/u-boot/20260612-split-id-table-into-vendor-files-v1-0-dfaaa82cc6f0@infineon.com/
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