[PATCH] arm: dts: socfpga: enforce MMC fifo-mode for high-memory access

[dinesh.maniyam at altera.com]

From: Dinesh Maniyam <dinesh.maniyam at altera.com>

DMA-based MMC transfers are limited to a 32-bit address space and can
fail when buffers are placed outside low memory. Enabling fifo-mode
disables DMA and allows U-Boot to reliably access MMC data from both
low and high DDR addresses using CPU-driven FIFO transfers.

This avoids future failures as the .wic image size has already reached
the current threshold and is expected to grow further, requiring
increased use of high-memory load addresses.

Applying this at the SoC DTSI level enforces consistent behavior across
all SoCFPGA-based products that uses the dw-mmc driver
and ensures reliable MMC access as image sizes increase
and high-memory buffer usage becomes unavoidable.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam at altera.com>
---
 arch/arm/dts/socfpga-common-u-boot.dtsi       | 4 ++++
 arch/arm/dts/socfpga_agilex-u-boot.dtsi       | 1 +
 arch/arm/dts/socfpga_arria10-u-boot.dtsi      | 4 ++++
 arch/arm/dts/socfpga_arria10_chameleonv3.dtsi | 1 +
 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi | 1 +
 arch/arm/dts/socfpga_n5x-u-boot.dtsi          | 1 +
 arch/arm/dts/socfpga_stratix10-u-boot.dtsi    | 4 ++++
 7 files changed, 16 insertions(+)

diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi
index ddef9a2896d..934f2bca505 100644
--- a/arch/arm/dts/socfpga-common-u-boot.dtsi
+++ b/arch/arm/dts/socfpga-common-u-boot.dtsi
@@ -33,3 +33,7 @@
 &sysmgr {
 	bootph-all;
 };
+
+&mmc {
+	fifo-mode;
+};
diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
index c0f932d0e11..3e98288af0e 100644
--- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
@@ -104,6 +104,7 @@
 
 &mmc {
 	resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
+	fifo-mode;
 };
 
 &porta {
diff --git a/arch/arm/dts/socfpga_arria10-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
index 2ed532ffb54..a5244706bad 100644
--- a/arch/arm/dts/socfpga_arria10-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
@@ -53,6 +53,10 @@
 	altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
 };
 
+&mmc {
+	fifo-mode;
+};
+
 &i2c0 {
 	reset-names = "i2c";
 };
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3.dtsi b/arch/arm/dts/socfpga_arria10_chameleonv3.dtsi
index 988cc445438..d5ec609d98d 100644
--- a/arch/arm/dts/socfpga_arria10_chameleonv3.dtsi
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3.dtsi
@@ -73,6 +73,7 @@
 };
 
 &mmc {
+	fifo-mode;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
index fee1fc39bb2..a5134557f1c 100644
--- a/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
+++ b/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
@@ -65,6 +65,7 @@
 	cap-sd-highspeed;
 	broken-cd;
 	bus-width = <4>;
+	fifo-mode;
 };
 
 &osc1 {
diff --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
index e27a64651e1..bb97412dcab 100644
--- a/arch/arm/dts/socfpga_n5x-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
@@ -92,6 +92,7 @@
 	clocks = <&clkmgr N5X_L4_MP_CLK>,
 		 <&clkmgr N5X_SDMMC_CLK>;
 	resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
+	fifo-mode;
 };
 
 &pdma {
diff --git a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
index 3e3a3780469..109ca41ee5c 100644
--- a/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_stratix10-u-boot.dtsi
@@ -6,3 +6,7 @@
  */
 
 #include "socfpga_soc64_fit-u-boot.dtsi"
+
+&mmc {
+	fifo-mode;
+};

base-commit: 70fd0c3bb7c26d42f24d10145dd5f3168ac92eac
-- 
2.43.7