[PATCH 1/4] arm: dts: socfpga: Update Arria 10 SoCDK U-Boot handoff data
dinesh.maniyam at altera.com
dinesh.maniyam at altera.com
Thu Jun 25 20:08:23 CEST 2026
From: Dinesh Maniyam <dinesh.maniyam at altera.com>
Update the U-Boot-only handoff data for the Arria 10 SoCDK platforms
and refresh the headers it generates.
Rename CONFIG_IO_* references to CFG_IO_* in the shared
arch/arm/dts/socfpga_arria10-handoff.dtsi consumer and in the two
existing Chameleon V3 handoff headers (270_3, 480_2) so that all
producers and consumers of the IO_* macros agree on the new
CFG_IO_* names. This also keeps the device tree compiler from
emitting "Unexpected 'CONFIG_IO_*'" lexical errors when building
the Arria 10 SoCDK and Chameleon V3 DTBs.
Update arch/arm/mach-socfpga/qts-filter-a10.sh so the generator
script emits CFG_IO_* macro names matching the consumer side.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam at altera.com>
---
arch/arm/dts/socfpga_arria10-handoff.dtsi | 36 +--
...ocfpga_arria10_chameleonv3_270_3_handoff.h | 250 +++++++-------
...ocfpga_arria10_chameleonv3_480_2_handoff.h | 250 +++++++-------
.../socfpga_arria10_socdk_nand-u-boot.dtsi | 42 +++
.../dts/socfpga_arria10_socdk_nand_handoff.h | 305 ++++++++++++++++++
.../socfpga_arria10_socdk_qspi-u-boot.dtsi | 48 +++
.../dts/socfpga_arria10_socdk_qspi_handoff.h | 305 ++++++++++++++++++
.../dts/socfpga_arria10_socdk_sdmmc_handoff.h | 262 +++++++--------
arch/arm/mach-socfpga/qts-filter-a10.sh | 22 +-
9 files changed, 1110 insertions(+), 410 deletions(-)
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_nand-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_nand_handoff.h
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_qspi-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.h
diff --git a/arch/arm/dts/socfpga_arria10-handoff.dtsi b/arch/arm/dts/socfpga_arria10-handoff.dtsi
index a3afb4d9df4..9405b15b4d5 100644
--- a/arch/arm/dts/socfpga_arria10-handoff.dtsi
+++ b/arch/arm/dts/socfpga_arria10-handoff.dtsi
@@ -189,24 +189,24 @@
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x003f3f3f>;
pinctrl-single,pins =
- <0x00000100 CONFIG_IO_BANK_VSEL>,
- <0x00000104 CONFIG_IO_MACRO (CONFIG_IO_1)>,
- <0x00000108 CONFIG_IO_MACRO (CONFIG_IO_2)>,
- <0x0000010c CONFIG_IO_MACRO (CONFIG_IO_3)>,
- <0x00000110 CONFIG_IO_MACRO (CONFIG_IO_4)>,
- <0x00000114 CONFIG_IO_MACRO (CONFIG_IO_5)>,
- <0x00000118 CONFIG_IO_MACRO (CONFIG_IO_6)>,
- <0x0000011c CONFIG_IO_MACRO (CONFIG_IO_7)>,
- <0x00000120 CONFIG_IO_MACRO (CONFIG_IO_8)>,
- <0x00000124 CONFIG_IO_MACRO (CONFIG_IO_9)>,
- <0x00000128 CONFIG_IO_MACRO (CONFIG_IO_10)>,
- <0x0000012c CONFIG_IO_MACRO (CONFIG_IO_11)>,
- <0x00000130 CONFIG_IO_MACRO (CONFIG_IO_12)>,
- <0x00000134 CONFIG_IO_MACRO (CONFIG_IO_13)>,
- <0x00000138 CONFIG_IO_MACRO (CONFIG_IO_14)>,
- <0x0000013c CONFIG_IO_MACRO (CONFIG_IO_15)>,
- <0x00000140 CONFIG_IO_MACRO (CONFIG_IO_16)>,
- <0x00000144 CONFIG_IO_MACRO (CONFIG_IO_17)>;
+ <0x00000100 CFG_IO_BANK_VSEL>,
+ <0x00000104 CFG_IO_MACRO (CFG_IO_1)>,
+ <0x00000108 CFG_IO_MACRO (CFG_IO_2)>,
+ <0x0000010c CFG_IO_MACRO (CFG_IO_3)>,
+ <0x00000110 CFG_IO_MACRO (CFG_IO_4)>,
+ <0x00000114 CFG_IO_MACRO (CFG_IO_5)>,
+ <0x00000118 CFG_IO_MACRO (CFG_IO_6)>,
+ <0x0000011c CFG_IO_MACRO (CFG_IO_7)>,
+ <0x00000120 CFG_IO_MACRO (CFG_IO_8)>,
+ <0x00000124 CFG_IO_MACRO (CFG_IO_9)>,
+ <0x00000128 CFG_IO_MACRO (CFG_IO_10)>,
+ <0x0000012c CFG_IO_MACRO (CFG_IO_11)>,
+ <0x00000130 CFG_IO_MACRO (CFG_IO_12)>,
+ <0x00000134 CFG_IO_MACRO (CFG_IO_13)>,
+ <0x00000138 CFG_IO_MACRO (CFG_IO_14)>,
+ <0x0000013c CFG_IO_MACRO (CFG_IO_15)>,
+ <0x00000140 CFG_IO_MACRO (CFG_IO_16)>,
+ <0x00000144 CFG_IO_MACRO (CFG_IO_17)>;
bootph-all;
};
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h
index 9d8f4a0dd38..697c9a32a8c 100644
--- a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h
@@ -76,127 +76,127 @@
(ALTERAGRP_NOCCLK_MAINCNT))
/* Pin Mux Configuration */
-#define CONFIG_IO_10_INPUT_BUF_EN 1
-#define CONFIG_IO_10_PD_DRV_STRG 10
-#define CONFIG_IO_10_PD_SLW_RT 1
-#define CONFIG_IO_10_PU_DRV_STRG 8
-#define CONFIG_IO_10_PU_SLW_RT 1
-#define CONFIG_IO_10_RTRIM 1
-#define CONFIG_IO_10_WK_PU_EN 0
-#define CONFIG_IO_11_INPUT_BUF_EN 1
-#define CONFIG_IO_11_PD_DRV_STRG 10
-#define CONFIG_IO_11_PD_SLW_RT 1
-#define CONFIG_IO_11_PU_DRV_STRG 8
-#define CONFIG_IO_11_PU_SLW_RT 1
-#define CONFIG_IO_11_RTRIM 1
-#define CONFIG_IO_11_WK_PU_EN 0
-#define CONFIG_IO_12_INPUT_BUF_EN 0
-#define CONFIG_IO_12_PD_DRV_STRG 0
-#define CONFIG_IO_12_PD_SLW_RT 0
-#define CONFIG_IO_12_PU_DRV_STRG 0
-#define CONFIG_IO_12_PU_SLW_RT 0
-#define CONFIG_IO_12_RTRIM 1
-#define CONFIG_IO_12_WK_PU_EN 1
-#define CONFIG_IO_13_INPUT_BUF_EN 0
-#define CONFIG_IO_13_PD_DRV_STRG 0
-#define CONFIG_IO_13_PD_SLW_RT 0
-#define CONFIG_IO_13_PU_DRV_STRG 0
-#define CONFIG_IO_13_PU_SLW_RT 0
-#define CONFIG_IO_13_RTRIM 1
-#define CONFIG_IO_13_WK_PU_EN 1
-#define CONFIG_IO_14_INPUT_BUF_EN 0
-#define CONFIG_IO_14_PD_DRV_STRG 0
-#define CONFIG_IO_14_PD_SLW_RT 0
-#define CONFIG_IO_14_PU_DRV_STRG 0
-#define CONFIG_IO_14_PU_SLW_RT 0
-#define CONFIG_IO_14_RTRIM 1
-#define CONFIG_IO_14_WK_PU_EN 1
-#define CONFIG_IO_15_INPUT_BUF_EN 0
-#define CONFIG_IO_15_PD_DRV_STRG 0
-#define CONFIG_IO_15_PD_SLW_RT 0
-#define CONFIG_IO_15_PU_DRV_STRG 0
-#define CONFIG_IO_15_PU_SLW_RT 0
-#define CONFIG_IO_15_RTRIM 1
-#define CONFIG_IO_15_WK_PU_EN 1
-#define CONFIG_IO_16_INPUT_BUF_EN 0
-#define CONFIG_IO_16_PD_DRV_STRG 10
-#define CONFIG_IO_16_PD_SLW_RT 1
-#define CONFIG_IO_16_PU_DRV_STRG 8
-#define CONFIG_IO_16_PU_SLW_RT 1
-#define CONFIG_IO_16_RTRIM 1
-#define CONFIG_IO_16_WK_PU_EN 0
-#define CONFIG_IO_17_INPUT_BUF_EN 1
-#define CONFIG_IO_17_PD_DRV_STRG 10
-#define CONFIG_IO_17_PD_SLW_RT 1
-#define CONFIG_IO_17_PU_DRV_STRG 8
-#define CONFIG_IO_17_PU_SLW_RT 1
-#define CONFIG_IO_17_RTRIM 1
-#define CONFIG_IO_17_WK_PU_EN 0
-#define CONFIG_IO_1_INPUT_BUF_EN 1
-#define CONFIG_IO_1_PD_DRV_STRG 10
-#define CONFIG_IO_1_PD_SLW_RT 0
-#define CONFIG_IO_1_PU_DRV_STRG 8
-#define CONFIG_IO_1_PU_SLW_RT 0
-#define CONFIG_IO_1_RTRIM 1
-#define CONFIG_IO_1_WK_PU_EN 1
-#define CONFIG_IO_2_INPUT_BUF_EN 1
-#define CONFIG_IO_2_PD_DRV_STRG 10
-#define CONFIG_IO_2_PD_SLW_RT 0
-#define CONFIG_IO_2_PU_DRV_STRG 8
-#define CONFIG_IO_2_PU_SLW_RT 0
-#define CONFIG_IO_2_RTRIM 1
-#define CONFIG_IO_2_WK_PU_EN 1
-#define CONFIG_IO_3_INPUT_BUF_EN 1
-#define CONFIG_IO_3_PD_DRV_STRG 10
-#define CONFIG_IO_3_PD_SLW_RT 0
-#define CONFIG_IO_3_PU_DRV_STRG 8
-#define CONFIG_IO_3_PU_SLW_RT 0
-#define CONFIG_IO_3_RTRIM 1
-#define CONFIG_IO_3_WK_PU_EN 1
-#define CONFIG_IO_4_INPUT_BUF_EN 1
-#define CONFIG_IO_4_PD_DRV_STRG 10
-#define CONFIG_IO_4_PD_SLW_RT 1
-#define CONFIG_IO_4_PU_DRV_STRG 8
-#define CONFIG_IO_4_PU_SLW_RT 1
-#define CONFIG_IO_4_RTRIM 1
-#define CONFIG_IO_4_WK_PU_EN 0
-#define CONFIG_IO_5_INPUT_BUF_EN 1
-#define CONFIG_IO_5_PD_DRV_STRG 10
-#define CONFIG_IO_5_PD_SLW_RT 1
-#define CONFIG_IO_5_PU_DRV_STRG 8
-#define CONFIG_IO_5_PU_SLW_RT 1
-#define CONFIG_IO_5_RTRIM 1
-#define CONFIG_IO_5_WK_PU_EN 0
-#define CONFIG_IO_6_INPUT_BUF_EN 0
-#define CONFIG_IO_6_PD_DRV_STRG 10
-#define CONFIG_IO_6_PD_SLW_RT 1
-#define CONFIG_IO_6_PU_DRV_STRG 8
-#define CONFIG_IO_6_PU_SLW_RT 1
-#define CONFIG_IO_6_RTRIM 1
-#define CONFIG_IO_6_WK_PU_EN 0
-#define CONFIG_IO_7_INPUT_BUF_EN 1
-#define CONFIG_IO_7_PD_DRV_STRG 10
-#define CONFIG_IO_7_PD_SLW_RT 1
-#define CONFIG_IO_7_PU_DRV_STRG 8
-#define CONFIG_IO_7_PU_SLW_RT 1
-#define CONFIG_IO_7_RTRIM 1
-#define CONFIG_IO_7_WK_PU_EN 0
-#define CONFIG_IO_8_INPUT_BUF_EN 1
-#define CONFIG_IO_8_PD_DRV_STRG 10
-#define CONFIG_IO_8_PD_SLW_RT 1
-#define CONFIG_IO_8_PU_DRV_STRG 8
-#define CONFIG_IO_8_PU_SLW_RT 1
-#define CONFIG_IO_8_RTRIM 1
-#define CONFIG_IO_8_WK_PU_EN 0
-#define CONFIG_IO_9_INPUT_BUF_EN 1
-#define CONFIG_IO_9_PD_DRV_STRG 10
-#define CONFIG_IO_9_PD_SLW_RT 1
-#define CONFIG_IO_9_PU_DRV_STRG 8
-#define CONFIG_IO_9_PU_SLW_RT 1
-#define CONFIG_IO_9_RTRIM 1
-#define CONFIG_IO_9_WK_PU_EN 0
-#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
-#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
+#define CFG_IO_10_INPUT_BUF_EN 1
+#define CFG_IO_10_PD_DRV_STRG 10
+#define CFG_IO_10_PD_SLW_RT 1
+#define CFG_IO_10_PU_DRV_STRG 8
+#define CFG_IO_10_PU_SLW_RT 1
+#define CFG_IO_10_RTRIM 1
+#define CFG_IO_10_WK_PU_EN 0
+#define CFG_IO_11_INPUT_BUF_EN 1
+#define CFG_IO_11_PD_DRV_STRG 10
+#define CFG_IO_11_PD_SLW_RT 1
+#define CFG_IO_11_PU_DRV_STRG 8
+#define CFG_IO_11_PU_SLW_RT 1
+#define CFG_IO_11_RTRIM 1
+#define CFG_IO_11_WK_PU_EN 0
+#define CFG_IO_12_INPUT_BUF_EN 0
+#define CFG_IO_12_PD_DRV_STRG 0
+#define CFG_IO_12_PD_SLW_RT 0
+#define CFG_IO_12_PU_DRV_STRG 0
+#define CFG_IO_12_PU_SLW_RT 0
+#define CFG_IO_12_RTRIM 1
+#define CFG_IO_12_WK_PU_EN 1
+#define CFG_IO_13_INPUT_BUF_EN 0
+#define CFG_IO_13_PD_DRV_STRG 0
+#define CFG_IO_13_PD_SLW_RT 0
+#define CFG_IO_13_PU_DRV_STRG 0
+#define CFG_IO_13_PU_SLW_RT 0
+#define CFG_IO_13_RTRIM 1
+#define CFG_IO_13_WK_PU_EN 1
+#define CFG_IO_14_INPUT_BUF_EN 0
+#define CFG_IO_14_PD_DRV_STRG 0
+#define CFG_IO_14_PD_SLW_RT 0
+#define CFG_IO_14_PU_DRV_STRG 0
+#define CFG_IO_14_PU_SLW_RT 0
+#define CFG_IO_14_RTRIM 1
+#define CFG_IO_14_WK_PU_EN 1
+#define CFG_IO_15_INPUT_BUF_EN 0
+#define CFG_IO_15_PD_DRV_STRG 0
+#define CFG_IO_15_PD_SLW_RT 0
+#define CFG_IO_15_PU_DRV_STRG 0
+#define CFG_IO_15_PU_SLW_RT 0
+#define CFG_IO_15_RTRIM 1
+#define CFG_IO_15_WK_PU_EN 1
+#define CFG_IO_16_INPUT_BUF_EN 0
+#define CFG_IO_16_PD_DRV_STRG 10
+#define CFG_IO_16_PD_SLW_RT 1
+#define CFG_IO_16_PU_DRV_STRG 8
+#define CFG_IO_16_PU_SLW_RT 1
+#define CFG_IO_16_RTRIM 1
+#define CFG_IO_16_WK_PU_EN 0
+#define CFG_IO_17_INPUT_BUF_EN 1
+#define CFG_IO_17_PD_DRV_STRG 10
+#define CFG_IO_17_PD_SLW_RT 1
+#define CFG_IO_17_PU_DRV_STRG 8
+#define CFG_IO_17_PU_SLW_RT 1
+#define CFG_IO_17_RTRIM 1
+#define CFG_IO_17_WK_PU_EN 0
+#define CFG_IO_1_INPUT_BUF_EN 1
+#define CFG_IO_1_PD_DRV_STRG 10
+#define CFG_IO_1_PD_SLW_RT 0
+#define CFG_IO_1_PU_DRV_STRG 8
+#define CFG_IO_1_PU_SLW_RT 0
+#define CFG_IO_1_RTRIM 1
+#define CFG_IO_1_WK_PU_EN 1
+#define CFG_IO_2_INPUT_BUF_EN 1
+#define CFG_IO_2_PD_DRV_STRG 10
+#define CFG_IO_2_PD_SLW_RT 0
+#define CFG_IO_2_PU_DRV_STRG 8
+#define CFG_IO_2_PU_SLW_RT 0
+#define CFG_IO_2_RTRIM 1
+#define CFG_IO_2_WK_PU_EN 1
+#define CFG_IO_3_INPUT_BUF_EN 1
+#define CFG_IO_3_PD_DRV_STRG 10
+#define CFG_IO_3_PD_SLW_RT 0
+#define CFG_IO_3_PU_DRV_STRG 8
+#define CFG_IO_3_PU_SLW_RT 0
+#define CFG_IO_3_RTRIM 1
+#define CFG_IO_3_WK_PU_EN 1
+#define CFG_IO_4_INPUT_BUF_EN 1
+#define CFG_IO_4_PD_DRV_STRG 10
+#define CFG_IO_4_PD_SLW_RT 1
+#define CFG_IO_4_PU_DRV_STRG 8
+#define CFG_IO_4_PU_SLW_RT 1
+#define CFG_IO_4_RTRIM 1
+#define CFG_IO_4_WK_PU_EN 0
+#define CFG_IO_5_INPUT_BUF_EN 1
+#define CFG_IO_5_PD_DRV_STRG 10
+#define CFG_IO_5_PD_SLW_RT 1
+#define CFG_IO_5_PU_DRV_STRG 8
+#define CFG_IO_5_PU_SLW_RT 1
+#define CFG_IO_5_RTRIM 1
+#define CFG_IO_5_WK_PU_EN 0
+#define CFG_IO_6_INPUT_BUF_EN 0
+#define CFG_IO_6_PD_DRV_STRG 10
+#define CFG_IO_6_PD_SLW_RT 1
+#define CFG_IO_6_PU_DRV_STRG 8
+#define CFG_IO_6_PU_SLW_RT 1
+#define CFG_IO_6_RTRIM 1
+#define CFG_IO_6_WK_PU_EN 0
+#define CFG_IO_7_INPUT_BUF_EN 1
+#define CFG_IO_7_PD_DRV_STRG 10
+#define CFG_IO_7_PD_SLW_RT 1
+#define CFG_IO_7_PU_DRV_STRG 8
+#define CFG_IO_7_PU_SLW_RT 1
+#define CFG_IO_7_RTRIM 1
+#define CFG_IO_7_WK_PU_EN 0
+#define CFG_IO_8_INPUT_BUF_EN 1
+#define CFG_IO_8_PD_DRV_STRG 10
+#define CFG_IO_8_PD_SLW_RT 1
+#define CFG_IO_8_PU_DRV_STRG 8
+#define CFG_IO_8_PU_SLW_RT 1
+#define CFG_IO_8_RTRIM 1
+#define CFG_IO_8_WK_PU_EN 0
+#define CFG_IO_9_INPUT_BUF_EN 1
+#define CFG_IO_9_PD_DRV_STRG 10
+#define CFG_IO_9_PD_SLW_RT 1
+#define CFG_IO_9_PU_DRV_STRG 8
+#define CFG_IO_9_PU_SLW_RT 1
+#define CFG_IO_9_RTRIM 1
+#define CFG_IO_9_WK_PU_EN 0
+#define CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
+#define CFG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
#define PINMUX_DEDICATED_IO_10_SEL 15
#define PINMUX_DEDICATED_IO_11_SEL 15
#define PINMUX_DEDICATED_IO_12_SEL 1
@@ -289,12 +289,12 @@
#define LWH2F_AXI_MASTER 1
/* Voltage Select for Config IO */
-#define CONFIG_IO_BANK_VSEL \
- (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
- (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
+#define CFG_IO_BANK_VSEL \
+ (((CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
+ (CFG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
/* Macro for Config IO bit mapping */
-#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
+#define CFG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
((NAME ## _WK_PU_EN & 0x1) << 16) | \
((NAME ## _PU_SLW_RT & 0x1) << 13) | \
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h
index caaff604eb8..df032bf843d 100644
--- a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h
@@ -76,127 +76,127 @@
(ALTERAGRP_NOCCLK_MAINCNT))
/* Pin Mux Configuration */
-#define CONFIG_IO_10_INPUT_BUF_EN 1
-#define CONFIG_IO_10_PD_DRV_STRG 10
-#define CONFIG_IO_10_PD_SLW_RT 1
-#define CONFIG_IO_10_PU_DRV_STRG 8
-#define CONFIG_IO_10_PU_SLW_RT 1
-#define CONFIG_IO_10_RTRIM 1
-#define CONFIG_IO_10_WK_PU_EN 0
-#define CONFIG_IO_11_INPUT_BUF_EN 1
-#define CONFIG_IO_11_PD_DRV_STRG 10
-#define CONFIG_IO_11_PD_SLW_RT 1
-#define CONFIG_IO_11_PU_DRV_STRG 8
-#define CONFIG_IO_11_PU_SLW_RT 1
-#define CONFIG_IO_11_RTRIM 1
-#define CONFIG_IO_11_WK_PU_EN 0
-#define CONFIG_IO_12_INPUT_BUF_EN 0
-#define CONFIG_IO_12_PD_DRV_STRG 0
-#define CONFIG_IO_12_PD_SLW_RT 0
-#define CONFIG_IO_12_PU_DRV_STRG 0
-#define CONFIG_IO_12_PU_SLW_RT 0
-#define CONFIG_IO_12_RTRIM 1
-#define CONFIG_IO_12_WK_PU_EN 1
-#define CONFIG_IO_13_INPUT_BUF_EN 0
-#define CONFIG_IO_13_PD_DRV_STRG 0
-#define CONFIG_IO_13_PD_SLW_RT 0
-#define CONFIG_IO_13_PU_DRV_STRG 0
-#define CONFIG_IO_13_PU_SLW_RT 0
-#define CONFIG_IO_13_RTRIM 1
-#define CONFIG_IO_13_WK_PU_EN 1
-#define CONFIG_IO_14_INPUT_BUF_EN 0
-#define CONFIG_IO_14_PD_DRV_STRG 0
-#define CONFIG_IO_14_PD_SLW_RT 0
-#define CONFIG_IO_14_PU_DRV_STRG 0
-#define CONFIG_IO_14_PU_SLW_RT 0
-#define CONFIG_IO_14_RTRIM 1
-#define CONFIG_IO_14_WK_PU_EN 1
-#define CONFIG_IO_15_INPUT_BUF_EN 0
-#define CONFIG_IO_15_PD_DRV_STRG 0
-#define CONFIG_IO_15_PD_SLW_RT 0
-#define CONFIG_IO_15_PU_DRV_STRG 0
-#define CONFIG_IO_15_PU_SLW_RT 0
-#define CONFIG_IO_15_RTRIM 1
-#define CONFIG_IO_15_WK_PU_EN 1
-#define CONFIG_IO_16_INPUT_BUF_EN 0
-#define CONFIG_IO_16_PD_DRV_STRG 10
-#define CONFIG_IO_16_PD_SLW_RT 1
-#define CONFIG_IO_16_PU_DRV_STRG 8
-#define CONFIG_IO_16_PU_SLW_RT 1
-#define CONFIG_IO_16_RTRIM 1
-#define CONFIG_IO_16_WK_PU_EN 0
-#define CONFIG_IO_17_INPUT_BUF_EN 1
-#define CONFIG_IO_17_PD_DRV_STRG 10
-#define CONFIG_IO_17_PD_SLW_RT 1
-#define CONFIG_IO_17_PU_DRV_STRG 8
-#define CONFIG_IO_17_PU_SLW_RT 1
-#define CONFIG_IO_17_RTRIM 1
-#define CONFIG_IO_17_WK_PU_EN 0
-#define CONFIG_IO_1_INPUT_BUF_EN 1
-#define CONFIG_IO_1_PD_DRV_STRG 10
-#define CONFIG_IO_1_PD_SLW_RT 0
-#define CONFIG_IO_1_PU_DRV_STRG 8
-#define CONFIG_IO_1_PU_SLW_RT 0
-#define CONFIG_IO_1_RTRIM 1
-#define CONFIG_IO_1_WK_PU_EN 1
-#define CONFIG_IO_2_INPUT_BUF_EN 1
-#define CONFIG_IO_2_PD_DRV_STRG 10
-#define CONFIG_IO_2_PD_SLW_RT 0
-#define CONFIG_IO_2_PU_DRV_STRG 8
-#define CONFIG_IO_2_PU_SLW_RT 0
-#define CONFIG_IO_2_RTRIM 1
-#define CONFIG_IO_2_WK_PU_EN 1
-#define CONFIG_IO_3_INPUT_BUF_EN 1
-#define CONFIG_IO_3_PD_DRV_STRG 10
-#define CONFIG_IO_3_PD_SLW_RT 0
-#define CONFIG_IO_3_PU_DRV_STRG 8
-#define CONFIG_IO_3_PU_SLW_RT 0
-#define CONFIG_IO_3_RTRIM 1
-#define CONFIG_IO_3_WK_PU_EN 1
-#define CONFIG_IO_4_INPUT_BUF_EN 1
-#define CONFIG_IO_4_PD_DRV_STRG 10
-#define CONFIG_IO_4_PD_SLW_RT 1
-#define CONFIG_IO_4_PU_DRV_STRG 8
-#define CONFIG_IO_4_PU_SLW_RT 1
-#define CONFIG_IO_4_RTRIM 1
-#define CONFIG_IO_4_WK_PU_EN 0
-#define CONFIG_IO_5_INPUT_BUF_EN 1
-#define CONFIG_IO_5_PD_DRV_STRG 10
-#define CONFIG_IO_5_PD_SLW_RT 1
-#define CONFIG_IO_5_PU_DRV_STRG 8
-#define CONFIG_IO_5_PU_SLW_RT 1
-#define CONFIG_IO_5_RTRIM 1
-#define CONFIG_IO_5_WK_PU_EN 0
-#define CONFIG_IO_6_INPUT_BUF_EN 0
-#define CONFIG_IO_6_PD_DRV_STRG 10
-#define CONFIG_IO_6_PD_SLW_RT 1
-#define CONFIG_IO_6_PU_DRV_STRG 8
-#define CONFIG_IO_6_PU_SLW_RT 1
-#define CONFIG_IO_6_RTRIM 1
-#define CONFIG_IO_6_WK_PU_EN 0
-#define CONFIG_IO_7_INPUT_BUF_EN 1
-#define CONFIG_IO_7_PD_DRV_STRG 10
-#define CONFIG_IO_7_PD_SLW_RT 1
-#define CONFIG_IO_7_PU_DRV_STRG 8
-#define CONFIG_IO_7_PU_SLW_RT 1
-#define CONFIG_IO_7_RTRIM 1
-#define CONFIG_IO_7_WK_PU_EN 0
-#define CONFIG_IO_8_INPUT_BUF_EN 1
-#define CONFIG_IO_8_PD_DRV_STRG 10
-#define CONFIG_IO_8_PD_SLW_RT 1
-#define CONFIG_IO_8_PU_DRV_STRG 8
-#define CONFIG_IO_8_PU_SLW_RT 1
-#define CONFIG_IO_8_RTRIM 1
-#define CONFIG_IO_8_WK_PU_EN 0
-#define CONFIG_IO_9_INPUT_BUF_EN 1
-#define CONFIG_IO_9_PD_DRV_STRG 10
-#define CONFIG_IO_9_PD_SLW_RT 1
-#define CONFIG_IO_9_PU_DRV_STRG 8
-#define CONFIG_IO_9_PU_SLW_RT 1
-#define CONFIG_IO_9_RTRIM 1
-#define CONFIG_IO_9_WK_PU_EN 0
-#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
-#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
+#define CFG_IO_10_INPUT_BUF_EN 1
+#define CFG_IO_10_PD_DRV_STRG 10
+#define CFG_IO_10_PD_SLW_RT 1
+#define CFG_IO_10_PU_DRV_STRG 8
+#define CFG_IO_10_PU_SLW_RT 1
+#define CFG_IO_10_RTRIM 1
+#define CFG_IO_10_WK_PU_EN 0
+#define CFG_IO_11_INPUT_BUF_EN 1
+#define CFG_IO_11_PD_DRV_STRG 10
+#define CFG_IO_11_PD_SLW_RT 1
+#define CFG_IO_11_PU_DRV_STRG 8
+#define CFG_IO_11_PU_SLW_RT 1
+#define CFG_IO_11_RTRIM 1
+#define CFG_IO_11_WK_PU_EN 0
+#define CFG_IO_12_INPUT_BUF_EN 0
+#define CFG_IO_12_PD_DRV_STRG 0
+#define CFG_IO_12_PD_SLW_RT 0
+#define CFG_IO_12_PU_DRV_STRG 0
+#define CFG_IO_12_PU_SLW_RT 0
+#define CFG_IO_12_RTRIM 1
+#define CFG_IO_12_WK_PU_EN 1
+#define CFG_IO_13_INPUT_BUF_EN 0
+#define CFG_IO_13_PD_DRV_STRG 0
+#define CFG_IO_13_PD_SLW_RT 0
+#define CFG_IO_13_PU_DRV_STRG 0
+#define CFG_IO_13_PU_SLW_RT 0
+#define CFG_IO_13_RTRIM 1
+#define CFG_IO_13_WK_PU_EN 1
+#define CFG_IO_14_INPUT_BUF_EN 0
+#define CFG_IO_14_PD_DRV_STRG 0
+#define CFG_IO_14_PD_SLW_RT 0
+#define CFG_IO_14_PU_DRV_STRG 0
+#define CFG_IO_14_PU_SLW_RT 0
+#define CFG_IO_14_RTRIM 1
+#define CFG_IO_14_WK_PU_EN 1
+#define CFG_IO_15_INPUT_BUF_EN 0
+#define CFG_IO_15_PD_DRV_STRG 0
+#define CFG_IO_15_PD_SLW_RT 0
+#define CFG_IO_15_PU_DRV_STRG 0
+#define CFG_IO_15_PU_SLW_RT 0
+#define CFG_IO_15_RTRIM 1
+#define CFG_IO_15_WK_PU_EN 1
+#define CFG_IO_16_INPUT_BUF_EN 0
+#define CFG_IO_16_PD_DRV_STRG 10
+#define CFG_IO_16_PD_SLW_RT 1
+#define CFG_IO_16_PU_DRV_STRG 8
+#define CFG_IO_16_PU_SLW_RT 1
+#define CFG_IO_16_RTRIM 1
+#define CFG_IO_16_WK_PU_EN 0
+#define CFG_IO_17_INPUT_BUF_EN 1
+#define CFG_IO_17_PD_DRV_STRG 10
+#define CFG_IO_17_PD_SLW_RT 1
+#define CFG_IO_17_PU_DRV_STRG 8
+#define CFG_IO_17_PU_SLW_RT 1
+#define CFG_IO_17_RTRIM 1
+#define CFG_IO_17_WK_PU_EN 0
+#define CFG_IO_1_INPUT_BUF_EN 1
+#define CFG_IO_1_PD_DRV_STRG 10
+#define CFG_IO_1_PD_SLW_RT 0
+#define CFG_IO_1_PU_DRV_STRG 8
+#define CFG_IO_1_PU_SLW_RT 0
+#define CFG_IO_1_RTRIM 1
+#define CFG_IO_1_WK_PU_EN 1
+#define CFG_IO_2_INPUT_BUF_EN 1
+#define CFG_IO_2_PD_DRV_STRG 10
+#define CFG_IO_2_PD_SLW_RT 0
+#define CFG_IO_2_PU_DRV_STRG 8
+#define CFG_IO_2_PU_SLW_RT 0
+#define CFG_IO_2_RTRIM 1
+#define CFG_IO_2_WK_PU_EN 1
+#define CFG_IO_3_INPUT_BUF_EN 1
+#define CFG_IO_3_PD_DRV_STRG 10
+#define CFG_IO_3_PD_SLW_RT 0
+#define CFG_IO_3_PU_DRV_STRG 8
+#define CFG_IO_3_PU_SLW_RT 0
+#define CFG_IO_3_RTRIM 1
+#define CFG_IO_3_WK_PU_EN 1
+#define CFG_IO_4_INPUT_BUF_EN 1
+#define CFG_IO_4_PD_DRV_STRG 10
+#define CFG_IO_4_PD_SLW_RT 1
+#define CFG_IO_4_PU_DRV_STRG 8
+#define CFG_IO_4_PU_SLW_RT 1
+#define CFG_IO_4_RTRIM 1
+#define CFG_IO_4_WK_PU_EN 0
+#define CFG_IO_5_INPUT_BUF_EN 1
+#define CFG_IO_5_PD_DRV_STRG 10
+#define CFG_IO_5_PD_SLW_RT 1
+#define CFG_IO_5_PU_DRV_STRG 8
+#define CFG_IO_5_PU_SLW_RT 1
+#define CFG_IO_5_RTRIM 1
+#define CFG_IO_5_WK_PU_EN 0
+#define CFG_IO_6_INPUT_BUF_EN 0
+#define CFG_IO_6_PD_DRV_STRG 10
+#define CFG_IO_6_PD_SLW_RT 1
+#define CFG_IO_6_PU_DRV_STRG 8
+#define CFG_IO_6_PU_SLW_RT 1
+#define CFG_IO_6_RTRIM 1
+#define CFG_IO_6_WK_PU_EN 0
+#define CFG_IO_7_INPUT_BUF_EN 1
+#define CFG_IO_7_PD_DRV_STRG 10
+#define CFG_IO_7_PD_SLW_RT 1
+#define CFG_IO_7_PU_DRV_STRG 8
+#define CFG_IO_7_PU_SLW_RT 1
+#define CFG_IO_7_RTRIM 1
+#define CFG_IO_7_WK_PU_EN 0
+#define CFG_IO_8_INPUT_BUF_EN 1
+#define CFG_IO_8_PD_DRV_STRG 10
+#define CFG_IO_8_PD_SLW_RT 1
+#define CFG_IO_8_PU_DRV_STRG 8
+#define CFG_IO_8_PU_SLW_RT 1
+#define CFG_IO_8_RTRIM 1
+#define CFG_IO_8_WK_PU_EN 0
+#define CFG_IO_9_INPUT_BUF_EN 1
+#define CFG_IO_9_PD_DRV_STRG 10
+#define CFG_IO_9_PD_SLW_RT 1
+#define CFG_IO_9_PU_DRV_STRG 8
+#define CFG_IO_9_PU_SLW_RT 1
+#define CFG_IO_9_RTRIM 1
+#define CFG_IO_9_WK_PU_EN 0
+#define CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
+#define CFG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
#define PINMUX_DEDICATED_IO_10_SEL 15
#define PINMUX_DEDICATED_IO_11_SEL 15
#define PINMUX_DEDICATED_IO_12_SEL 1
@@ -289,12 +289,12 @@
#define LWH2F_AXI_MASTER 1
/* Voltage Select for Config IO */
-#define CONFIG_IO_BANK_VSEL \
- (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
- (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
+#define CFG_IO_BANK_VSEL \
+ (((CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
+ (CFG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
/* Macro for Config IO bit mapping */
-#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
+#define CFG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
((NAME ## _WK_PU_EN & 0x1) << 16) | \
((NAME ## _PU_SLW_RT & 0x1) << 13) | \
diff --git a/arch/arm/dts/socfpga_arria10_socdk_nand-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_socdk_nand-u-boot.dtsi
new file mode 100644
index 00000000000..e716bec041e
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk_nand-u-boot.dtsi
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 Altera Corporation
+ */
+
+#include "socfpga_arria10_socdk_nand_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10_socdk-u-boot.dtsi"
+
+/ {
+ fs_loader0: fs-loader {
+ bootph-all;
+ compatible = "u-boot,fs-loader";
+ };
+};
+
+&fpga_mgr {
+ bootph-all;
+ firmware-loader = <&fs_loader0>;
+ altr,bitstream = "300000";
+};
+
+&l4_mp_clk {
+ bootph-all;
+};
+
+&nand_x_clk {
+ bootph-all;
+};
+
+&nand_ecc_clk {
+ bootph-all;
+};
+
+&nand_clk {
+ bootph-all;
+};
+
+&nand {
+ bootph-all;
+};
diff --git a/arch/arm/dts/socfpga_arria10_socdk_nand_handoff.h b/arch/arm/dts/socfpga_arria10_socdk_nand_handoff.h
new file mode 100644
index 00000000000..308579b7fe3
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk_nand_handoff.h
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera Arria 10 SoCFPGA configuration
+ */
+
+#ifndef __SOCFPGA_ARRIA10_CFG_H__
+#define __SOCFPGA_ARRIA10_CFG_H__
+
+/* Clocks */
+#define CB_INTOSC_LS_CLK_HZ 60000000
+#define EMAC0_CLK_HZ 250000000
+#define EMAC1_CLK_HZ 250000000
+#define EMAC2_CLK_HZ 250000000
+#define EOSC1_CLK_HZ 25000000
+#define F2H_FREE_CLK_HZ 200000000
+#define H2F_USER0_CLK_HZ 400000000
+#define H2F_USER1_CLK_HZ 400000000
+#define L3_MAIN_FREE_CLK_HZ 200000000
+#define SDMMC_CLK_HZ 200000000
+#define TPIU_CLK_HZ 100000000
+#define MAINPLLGRP_CNTR15CLK_CNT 900
+#define MAINPLLGRP_CNTR2CLK_CNT 900
+#define MAINPLLGRP_CNTR3CLK_CNT 900
+#define MAINPLLGRP_CNTR4CLK_CNT 900
+#define MAINPLLGRP_CNTR5CLK_CNT 900
+#define MAINPLLGRP_CNTR6CLK_CNT 900
+#define MAINPLLGRP_CNTR7CLK_CNT 900
+#define MAINPLLGRP_CNTR7CLK_SRC 0
+#define MAINPLLGRP_CNTR8CLK_CNT 900
+#define MAINPLLGRP_CNTR9CLK_CNT 900
+#define MAINPLLGRP_CNTR9CLK_SRC 0
+#define MAINPLLGRP_MPUCLK_CNT 0
+#define MAINPLLGRP_MPUCLK_SRC 0
+#define MAINPLLGRP_NOCCLK_CNT 0
+#define MAINPLLGRP_NOCCLK_SRC 0
+#define MAINPLLGRP_NOCDIV_CSATCLK 0
+#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1
+#define MAINPLLGRP_NOCDIV_CSTRACECLK 1
+#define MAINPLLGRP_NOCDIV_L4MAINCLK 0
+#define MAINPLLGRP_NOCDIV_L4MPCLK 0
+#define MAINPLLGRP_NOCDIV_L4SPCLK 2
+#define MAINPLLGRP_VCO0_PSRC 0
+#define MAINPLLGRP_VCO1_DENOM 1
+#define MAINPLLGRP_VCO1_NUMER 191
+#define PERPLLGRP_CNTR2CLK_CNT 7
+#define PERPLLGRP_CNTR2CLK_SRC 1
+#define PERPLLGRP_CNTR3CLK_CNT 900
+#define PERPLLGRP_CNTR3CLK_SRC 1
+#define PERPLLGRP_CNTR4CLK_CNT 19
+#define PERPLLGRP_CNTR4CLK_SRC 1
+#define PERPLLGRP_CNTR5CLK_CNT 499
+#define PERPLLGRP_CNTR5CLK_SRC 1
+#define PERPLLGRP_CNTR6CLK_CNT 900
+#define PERPLLGRP_CNTR6CLK_SRC 1
+#define PERPLLGRP_CNTR7CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_SRC 0
+#define PERPLLGRP_CNTR9CLK_CNT 900
+#define PERPLLGRP_EMACCTL_EMAC0SEL 0
+#define PERPLLGRP_EMACCTL_EMAC1SEL 0
+#define PERPLLGRP_EMACCTL_EMAC2SEL 0
+#define PERPLLGRP_GPIODIV_GPIODBCLK 32000
+#define PERPLLGRP_VCO0_PSRC 0
+#define PERPLLGRP_VCO1_DENOM 1
+#define PERPLLGRP_VCO1_NUMER 159
+#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16
+#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8
+#define CLKMGR_TESTIOCTRL_PERICLKSEL 8
+#define ALTERAGRP_MPUCLK_MAINCNT 1
+#define ALTERAGRP_MPUCLK_PERICNT 900
+#define ALTERAGRP_NOCCLK_MAINCNT 11
+#define ALTERAGRP_NOCCLK_PERICNT 900
+#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
+ (ALTERAGRP_MPUCLK_MAINCNT))
+#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \
+ (ALTERAGRP_NOCCLK_MAINCNT))
+
+/* Pin Mux Configuration */
+#define CFG_IO_10_INPUT_BUF_EN 0
+#define CFG_IO_10_PD_DRV_STRG 10
+#define CFG_IO_10_PD_SLW_RT 1
+#define CFG_IO_10_PU_DRV_STRG 8
+#define CFG_IO_10_PU_SLW_RT 1
+#define CFG_IO_10_RTRIM 1
+#define CFG_IO_10_WK_PU_EN 0
+#define CFG_IO_11_INPUT_BUF_EN 0
+#define CFG_IO_11_PD_DRV_STRG 10
+#define CFG_IO_11_PD_SLW_RT 1
+#define CFG_IO_11_PU_DRV_STRG 8
+#define CFG_IO_11_PU_SLW_RT 1
+#define CFG_IO_11_RTRIM 1
+#define CFG_IO_11_WK_PU_EN 0
+#define CFG_IO_12_INPUT_BUF_EN 1
+#define CFG_IO_12_PD_DRV_STRG 10
+#define CFG_IO_12_PD_SLW_RT 1
+#define CFG_IO_12_PU_DRV_STRG 8
+#define CFG_IO_12_PU_SLW_RT 1
+#define CFG_IO_12_RTRIM 1
+#define CFG_IO_12_WK_PU_EN 0
+#define CFG_IO_13_INPUT_BUF_EN 0
+#define CFG_IO_13_PD_DRV_STRG 10
+#define CFG_IO_13_PD_SLW_RT 1
+#define CFG_IO_13_PU_DRV_STRG 8
+#define CFG_IO_13_PU_SLW_RT 1
+#define CFG_IO_13_RTRIM 1
+#define CFG_IO_13_WK_PU_EN 0
+#define CFG_IO_14_INPUT_BUF_EN 1
+#define CFG_IO_14_PD_DRV_STRG 10
+#define CFG_IO_14_PD_SLW_RT 1
+#define CFG_IO_14_PU_DRV_STRG 8
+#define CFG_IO_14_PU_SLW_RT 1
+#define CFG_IO_14_RTRIM 1
+#define CFG_IO_14_WK_PU_EN 0
+#define CFG_IO_15_INPUT_BUF_EN 1
+#define CFG_IO_15_PD_DRV_STRG 10
+#define CFG_IO_15_PD_SLW_RT 1
+#define CFG_IO_15_PU_DRV_STRG 8
+#define CFG_IO_15_PU_SLW_RT 1
+#define CFG_IO_15_RTRIM 1
+#define CFG_IO_15_WK_PU_EN 0
+#define CFG_IO_16_INPUT_BUF_EN 1
+#define CFG_IO_16_PD_DRV_STRG 10
+#define CFG_IO_16_PD_SLW_RT 1
+#define CFG_IO_16_PU_DRV_STRG 8
+#define CFG_IO_16_PU_SLW_RT 1
+#define CFG_IO_16_RTRIM 1
+#define CFG_IO_16_WK_PU_EN 0
+#define CFG_IO_17_INPUT_BUF_EN 1
+#define CFG_IO_17_PD_DRV_STRG 10
+#define CFG_IO_17_PD_SLW_RT 1
+#define CFG_IO_17_PU_DRV_STRG 8
+#define CFG_IO_17_PU_SLW_RT 1
+#define CFG_IO_17_RTRIM 1
+#define CFG_IO_17_WK_PU_EN 0
+#define CFG_IO_1_INPUT_BUF_EN 1
+#define CFG_IO_1_PD_DRV_STRG 10
+#define CFG_IO_1_PD_SLW_RT 0
+#define CFG_IO_1_PU_DRV_STRG 8
+#define CFG_IO_1_PU_SLW_RT 0
+#define CFG_IO_1_RTRIM 1
+#define CFG_IO_1_WK_PU_EN 1
+#define CFG_IO_2_INPUT_BUF_EN 1
+#define CFG_IO_2_PD_DRV_STRG 10
+#define CFG_IO_2_PD_SLW_RT 0
+#define CFG_IO_2_PU_DRV_STRG 8
+#define CFG_IO_2_PU_SLW_RT 0
+#define CFG_IO_2_RTRIM 1
+#define CFG_IO_2_WK_PU_EN 1
+#define CFG_IO_3_INPUT_BUF_EN 1
+#define CFG_IO_3_PD_DRV_STRG 10
+#define CFG_IO_3_PD_SLW_RT 0
+#define CFG_IO_3_PU_DRV_STRG 8
+#define CFG_IO_3_PU_SLW_RT 0
+#define CFG_IO_3_RTRIM 1
+#define CFG_IO_3_WK_PU_EN 1
+#define CFG_IO_4_INPUT_BUF_EN 1
+#define CFG_IO_4_PD_DRV_STRG 10
+#define CFG_IO_4_PD_SLW_RT 1
+#define CFG_IO_4_PU_DRV_STRG 8
+#define CFG_IO_4_PU_SLW_RT 1
+#define CFG_IO_4_RTRIM 1
+#define CFG_IO_4_WK_PU_EN 0
+#define CFG_IO_5_INPUT_BUF_EN 1
+#define CFG_IO_5_PD_DRV_STRG 10
+#define CFG_IO_5_PD_SLW_RT 1
+#define CFG_IO_5_PU_DRV_STRG 8
+#define CFG_IO_5_PU_SLW_RT 1
+#define CFG_IO_5_RTRIM 1
+#define CFG_IO_5_WK_PU_EN 0
+#define CFG_IO_6_INPUT_BUF_EN 0
+#define CFG_IO_6_PD_DRV_STRG 10
+#define CFG_IO_6_PD_SLW_RT 1
+#define CFG_IO_6_PU_DRV_STRG 8
+#define CFG_IO_6_PU_SLW_RT 1
+#define CFG_IO_6_RTRIM 1
+#define CFG_IO_6_WK_PU_EN 0
+#define CFG_IO_7_INPUT_BUF_EN 0
+#define CFG_IO_7_PD_DRV_STRG 10
+#define CFG_IO_7_PD_SLW_RT 1
+#define CFG_IO_7_PU_DRV_STRG 8
+#define CFG_IO_7_PU_SLW_RT 1
+#define CFG_IO_7_RTRIM 1
+#define CFG_IO_7_WK_PU_EN 0
+#define CFG_IO_8_INPUT_BUF_EN 1
+#define CFG_IO_8_PD_DRV_STRG 10
+#define CFG_IO_8_PD_SLW_RT 1
+#define CFG_IO_8_PU_DRV_STRG 8
+#define CFG_IO_8_PU_SLW_RT 1
+#define CFG_IO_8_RTRIM 1
+#define CFG_IO_8_WK_PU_EN 0
+#define CFG_IO_9_INPUT_BUF_EN 1
+#define CFG_IO_9_PD_DRV_STRG 10
+#define CFG_IO_9_PD_SLW_RT 1
+#define CFG_IO_9_PU_DRV_STRG 8
+#define CFG_IO_9_PU_SLW_RT 1
+#define CFG_IO_9_RTRIM 1
+#define CFG_IO_9_WK_PU_EN 0
+#define CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
+#define CFG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
+#define PINMUX_DEDICATED_IO_10_SEL 14
+#define PINMUX_DEDICATED_IO_11_SEL 14
+#define PINMUX_DEDICATED_IO_12_SEL 14
+#define PINMUX_DEDICATED_IO_13_SEL 14
+#define PINMUX_DEDICATED_IO_14_SEL 14
+#define PINMUX_DEDICATED_IO_15_SEL 14
+#define PINMUX_DEDICATED_IO_16_SEL 14
+#define PINMUX_DEDICATED_IO_17_SEL 14
+#define PINMUX_DEDICATED_IO_4_SEL 14
+#define PINMUX_DEDICATED_IO_5_SEL 14
+#define PINMUX_DEDICATED_IO_6_SEL 14
+#define PINMUX_DEDICATED_IO_7_SEL 14
+#define PINMUX_DEDICATED_IO_8_SEL 14
+#define PINMUX_DEDICATED_IO_9_SEL 14
+#define PINMUX_I2C0_USEFPGA_SEL 0
+#define PINMUX_I2C1_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC0_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC1_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC2_USEFPGA_SEL 0
+#define PINMUX_NAND_USEFPGA_SEL 0
+#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0
+#define PINMUX_QSPI_USEFPGA_SEL 0
+#define PINMUX_RGMII0_USEFPGA_SEL 0
+#define PINMUX_RGMII1_USEFPGA_SEL 0
+#define PINMUX_RGMII2_USEFPGA_SEL 0
+#define PINMUX_SDMMC_USEFPGA_SEL 0
+#define PINMUX_SHARED_IO_Q1_10_SEL 8
+#define PINMUX_SHARED_IO_Q1_11_SEL 8
+#define PINMUX_SHARED_IO_Q1_12_SEL 8
+#define PINMUX_SHARED_IO_Q1_1_SEL 8
+#define PINMUX_SHARED_IO_Q1_2_SEL 8
+#define PINMUX_SHARED_IO_Q1_3_SEL 8
+#define PINMUX_SHARED_IO_Q1_4_SEL 8
+#define PINMUX_SHARED_IO_Q1_5_SEL 8
+#define PINMUX_SHARED_IO_Q1_6_SEL 8
+#define PINMUX_SHARED_IO_Q1_7_SEL 8
+#define PINMUX_SHARED_IO_Q1_8_SEL 8
+#define PINMUX_SHARED_IO_Q1_9_SEL 8
+#define PINMUX_SHARED_IO_Q2_10_SEL 4
+#define PINMUX_SHARED_IO_Q2_11_SEL 4
+#define PINMUX_SHARED_IO_Q2_12_SEL 4
+#define PINMUX_SHARED_IO_Q2_1_SEL 4
+#define PINMUX_SHARED_IO_Q2_2_SEL 4
+#define PINMUX_SHARED_IO_Q2_3_SEL 4
+#define PINMUX_SHARED_IO_Q2_4_SEL 4
+#define PINMUX_SHARED_IO_Q2_5_SEL 4
+#define PINMUX_SHARED_IO_Q2_6_SEL 4
+#define PINMUX_SHARED_IO_Q2_7_SEL 4
+#define PINMUX_SHARED_IO_Q2_8_SEL 4
+#define PINMUX_SHARED_IO_Q2_9_SEL 4
+#define PINMUX_SHARED_IO_Q3_10_SEL 10
+#define PINMUX_SHARED_IO_Q3_11_SEL 1
+#define PINMUX_SHARED_IO_Q3_12_SEL 1
+#define PINMUX_SHARED_IO_Q3_1_SEL 3
+#define PINMUX_SHARED_IO_Q3_2_SEL 3
+#define PINMUX_SHARED_IO_Q3_3_SEL 3
+#define PINMUX_SHARED_IO_Q3_4_SEL 3
+#define PINMUX_SHARED_IO_Q3_5_SEL 3
+#define PINMUX_SHARED_IO_Q3_6_SEL 15
+#define PINMUX_SHARED_IO_Q3_7_SEL 13
+#define PINMUX_SHARED_IO_Q3_8_SEL 13
+#define PINMUX_SHARED_IO_Q3_9_SEL 10
+#define PINMUX_SHARED_IO_Q4_10_SEL 12
+#define PINMUX_SHARED_IO_Q4_11_SEL 12
+#define PINMUX_SHARED_IO_Q4_12_SEL 12
+#define PINMUX_SHARED_IO_Q4_1_SEL 0
+#define PINMUX_SHARED_IO_Q4_2_SEL 0
+#define PINMUX_SHARED_IO_Q4_3_SEL 15
+#define PINMUX_SHARED_IO_Q4_4_SEL 12
+#define PINMUX_SHARED_IO_Q4_5_SEL 15
+#define PINMUX_SHARED_IO_Q4_6_SEL 15
+#define PINMUX_SHARED_IO_Q4_7_SEL 10
+#define PINMUX_SHARED_IO_Q4_8_SEL 15
+#define PINMUX_SHARED_IO_Q4_9_SEL 12
+#define PINMUX_SPIM0_USEFPGA_SEL 0
+#define PINMUX_SPIM1_USEFPGA_SEL 0
+#define PINMUX_SPIS0_USEFPGA_SEL 0
+#define PINMUX_SPIS1_USEFPGA_SEL 0
+#define PINMUX_UART0_USEFPGA_SEL 0
+#define PINMUX_UART1_USEFPGA_SEL 0
+#define PINMUX_USB0_USEFPGA_SEL 0
+#define PINMUX_USB1_USEFPGA_SEL 0
+
+/* Bridge Configuration */
+#define F2H_AXI_SLAVE 1
+#define F2SDRAM0_AXI_SLAVE 1
+#define F2SDRAM1_AXI_SLAVE 0
+#define F2SDRAM2_AXI_SLAVE 1
+#define H2F_AXI_MASTER 1
+#define LWH2F_AXI_MASTER 1
+
+/* Voltage Select for CFG IO */
+#define CFG_IO_BANK_VSEL \
+ (((CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
+ (CFG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
+
+/* Macro for CFG IO bit mapping */
+#define CFG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
+ ((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
+ ((NAME ## _WK_PU_EN & 0x1) << 16) | \
+ ((NAME ## _PU_SLW_RT & 0x1) << 13) | \
+ ((NAME ## _PU_DRV_STRG & 0xf) << 8) | \
+ ((NAME ## _PD_SLW_RT & 0x1) << 5) | \
+ (NAME ## _PD_DRV_STRG & 0x1f))
+
+#endif /* __SOCFPGA_ARRIA10_CFG_H__ */
diff --git a/arch/arm/dts/socfpga_arria10_socdk_qspi-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_socdk_qspi-u-boot.dtsi
new file mode 100644
index 00000000000..a38a0fd2411
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk_qspi-u-boot.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright (C) 2022 Altera Corporation
+ *
+ * These codes were based on handoffs
+ * generated from both Qsys and Quartus.
+ */
+
+#include "socfpga_arria10_socdk_qspi_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10_socdk-u-boot.dtsi"
+
+/ {
+ aliases {
+ spi0 = &qspi;
+ };
+
+ fs_loader0: fs-loader {
+ bootph-all;
+ compatible = "u-boot,fs-loader";
+ sfconfig = <0 0 100000000 3>;
+ };
+};
+
+&fpga_mgr {
+ bootph-all;
+ firmware-loader = <&fs_loader0>;
+ altr,bitstream = "300000";
+};
+
+&l4_main_clk {
+ bootph-all;
+};
+
+&qspi_clk {
+ bootph-all;
+};
+
+&qspi {
+ bootph-all;
+
+ flash0: n25q00a at 0 {
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ /delete-property/ cdns,read-delay;
+ };
+};
diff --git a/arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.h b/arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.h
new file mode 100644
index 00000000000..64af51cf26b
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.h
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera Arria 10 SoCFPGA configuration
+ */
+
+#ifndef __SOCFPGA_ARRIA10_CFG_H__
+#define __SOCFPGA_ARRIA10_CFG_H__
+
+/* Clocks */
+#define CB_INTOSC_LS_CLK_HZ 60000000
+#define EMAC0_CLK_HZ 250000000
+#define EMAC1_CLK_HZ 250000000
+#define EMAC2_CLK_HZ 250000000
+#define EOSC1_CLK_HZ 25000000
+#define F2H_FREE_CLK_HZ 200000000
+#define H2F_USER0_CLK_HZ 400000000
+#define H2F_USER1_CLK_HZ 400000000
+#define L3_MAIN_FREE_CLK_HZ 200000000
+#define SDMMC_CLK_HZ 200000000
+#define TPIU_CLK_HZ 100000000
+#define MAINPLLGRP_CNTR15CLK_CNT 900
+#define MAINPLLGRP_CNTR2CLK_CNT 900
+#define MAINPLLGRP_CNTR3CLK_CNT 900
+#define MAINPLLGRP_CNTR4CLK_CNT 900
+#define MAINPLLGRP_CNTR5CLK_CNT 900
+#define MAINPLLGRP_CNTR6CLK_CNT 900
+#define MAINPLLGRP_CNTR7CLK_CNT 900
+#define MAINPLLGRP_CNTR7CLK_SRC 0
+#define MAINPLLGRP_CNTR8CLK_CNT 900
+#define MAINPLLGRP_CNTR9CLK_CNT 900
+#define MAINPLLGRP_CNTR9CLK_SRC 0
+#define MAINPLLGRP_MPUCLK_CNT 0
+#define MAINPLLGRP_MPUCLK_SRC 0
+#define MAINPLLGRP_NOCCLK_CNT 0
+#define MAINPLLGRP_NOCCLK_SRC 0
+#define MAINPLLGRP_NOCDIV_CSATCLK 0
+#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1
+#define MAINPLLGRP_NOCDIV_CSTRACECLK 1
+#define MAINPLLGRP_NOCDIV_L4MAINCLK 0
+#define MAINPLLGRP_NOCDIV_L4MPCLK 0
+#define MAINPLLGRP_NOCDIV_L4SPCLK 2
+#define MAINPLLGRP_VCO0_PSRC 0
+#define MAINPLLGRP_VCO1_DENOM 1
+#define MAINPLLGRP_VCO1_NUMER 191
+#define PERPLLGRP_CNTR2CLK_CNT 7
+#define PERPLLGRP_CNTR2CLK_SRC 1
+#define PERPLLGRP_CNTR3CLK_CNT 900
+#define PERPLLGRP_CNTR3CLK_SRC 1
+#define PERPLLGRP_CNTR4CLK_CNT 19
+#define PERPLLGRP_CNTR4CLK_SRC 1
+#define PERPLLGRP_CNTR5CLK_CNT 499
+#define PERPLLGRP_CNTR5CLK_SRC 1
+#define PERPLLGRP_CNTR6CLK_CNT 900
+#define PERPLLGRP_CNTR6CLK_SRC 1
+#define PERPLLGRP_CNTR7CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_SRC 0
+#define PERPLLGRP_CNTR9CLK_CNT 900
+#define PERPLLGRP_EMACCTL_EMAC0SEL 0
+#define PERPLLGRP_EMACCTL_EMAC1SEL 0
+#define PERPLLGRP_EMACCTL_EMAC2SEL 0
+#define PERPLLGRP_GPIODIV_GPIODBCLK 32000
+#define PERPLLGRP_VCO0_PSRC 0
+#define PERPLLGRP_VCO1_DENOM 1
+#define PERPLLGRP_VCO1_NUMER 159
+#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16
+#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8
+#define CLKMGR_TESTIOCTRL_PERICLKSEL 8
+#define ALTERAGRP_MPUCLK_MAINCNT 1
+#define ALTERAGRP_MPUCLK_PERICNT 900
+#define ALTERAGRP_NOCCLK_MAINCNT 11
+#define ALTERAGRP_NOCCLK_PERICNT 900
+#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
+ (ALTERAGRP_MPUCLK_MAINCNT))
+#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \
+ (ALTERAGRP_NOCCLK_MAINCNT))
+
+/* Pin Mux Configuration */
+#define CFG_IO_10_INPUT_BUF_EN 0
+#define CFG_IO_10_PD_DRV_STRG 0
+#define CFG_IO_10_PD_SLW_RT 0
+#define CFG_IO_10_PU_DRV_STRG 0
+#define CFG_IO_10_PU_SLW_RT 0
+#define CFG_IO_10_RTRIM 1
+#define CFG_IO_10_WK_PU_EN 1
+#define CFG_IO_11_INPUT_BUF_EN 0
+#define CFG_IO_11_PD_DRV_STRG 0
+#define CFG_IO_11_PD_SLW_RT 0
+#define CFG_IO_11_PU_DRV_STRG 0
+#define CFG_IO_11_PU_SLW_RT 0
+#define CFG_IO_11_RTRIM 1
+#define CFG_IO_11_WK_PU_EN 1
+#define CFG_IO_12_INPUT_BUF_EN 0
+#define CFG_IO_12_PD_DRV_STRG 0
+#define CFG_IO_12_PD_SLW_RT 0
+#define CFG_IO_12_PU_DRV_STRG 0
+#define CFG_IO_12_PU_SLW_RT 0
+#define CFG_IO_12_RTRIM 1
+#define CFG_IO_12_WK_PU_EN 1
+#define CFG_IO_13_INPUT_BUF_EN 0
+#define CFG_IO_13_PD_DRV_STRG 0
+#define CFG_IO_13_PD_SLW_RT 0
+#define CFG_IO_13_PU_DRV_STRG 0
+#define CFG_IO_13_PU_SLW_RT 0
+#define CFG_IO_13_RTRIM 1
+#define CFG_IO_13_WK_PU_EN 1
+#define CFG_IO_14_INPUT_BUF_EN 0
+#define CFG_IO_14_PD_DRV_STRG 0
+#define CFG_IO_14_PD_SLW_RT 0
+#define CFG_IO_14_PU_DRV_STRG 0
+#define CFG_IO_14_PU_SLW_RT 0
+#define CFG_IO_14_RTRIM 1
+#define CFG_IO_14_WK_PU_EN 1
+#define CFG_IO_15_INPUT_BUF_EN 0
+#define CFG_IO_15_PD_DRV_STRG 0
+#define CFG_IO_15_PD_SLW_RT 0
+#define CFG_IO_15_PU_DRV_STRG 0
+#define CFG_IO_15_PU_SLW_RT 0
+#define CFG_IO_15_RTRIM 1
+#define CFG_IO_15_WK_PU_EN 1
+#define CFG_IO_16_INPUT_BUF_EN 0
+#define CFG_IO_16_PD_DRV_STRG 10
+#define CFG_IO_16_PD_SLW_RT 1
+#define CFG_IO_16_PU_DRV_STRG 8
+#define CFG_IO_16_PU_SLW_RT 1
+#define CFG_IO_16_RTRIM 1
+#define CFG_IO_16_WK_PU_EN 0
+#define CFG_IO_17_INPUT_BUF_EN 1
+#define CFG_IO_17_PD_DRV_STRG 10
+#define CFG_IO_17_PD_SLW_RT 1
+#define CFG_IO_17_PU_DRV_STRG 8
+#define CFG_IO_17_PU_SLW_RT 1
+#define CFG_IO_17_RTRIM 1
+#define CFG_IO_17_WK_PU_EN 0
+#define CFG_IO_1_INPUT_BUF_EN 1
+#define CFG_IO_1_PD_DRV_STRG 10
+#define CFG_IO_1_PD_SLW_RT 0
+#define CFG_IO_1_PU_DRV_STRG 8
+#define CFG_IO_1_PU_SLW_RT 0
+#define CFG_IO_1_RTRIM 1
+#define CFG_IO_1_WK_PU_EN 1
+#define CFG_IO_2_INPUT_BUF_EN 1
+#define CFG_IO_2_PD_DRV_STRG 10
+#define CFG_IO_2_PD_SLW_RT 0
+#define CFG_IO_2_PU_DRV_STRG 8
+#define CFG_IO_2_PU_SLW_RT 0
+#define CFG_IO_2_RTRIM 1
+#define CFG_IO_2_WK_PU_EN 1
+#define CFG_IO_3_INPUT_BUF_EN 1
+#define CFG_IO_3_PD_DRV_STRG 10
+#define CFG_IO_3_PD_SLW_RT 0
+#define CFG_IO_3_PU_DRV_STRG 8
+#define CFG_IO_3_PU_SLW_RT 0
+#define CFG_IO_3_RTRIM 1
+#define CFG_IO_3_WK_PU_EN 1
+#define CFG_IO_4_INPUT_BUF_EN 0
+#define CFG_IO_4_PD_DRV_STRG 10
+#define CFG_IO_4_PD_SLW_RT 1
+#define CFG_IO_4_PU_DRV_STRG 8
+#define CFG_IO_4_PU_SLW_RT 1
+#define CFG_IO_4_RTRIM 1
+#define CFG_IO_4_WK_PU_EN 0
+#define CFG_IO_5_INPUT_BUF_EN 1
+#define CFG_IO_5_PD_DRV_STRG 10
+#define CFG_IO_5_PD_SLW_RT 1
+#define CFG_IO_5_PU_DRV_STRG 8
+#define CFG_IO_5_PU_SLW_RT 1
+#define CFG_IO_5_RTRIM 1
+#define CFG_IO_5_WK_PU_EN 0
+#define CFG_IO_6_INPUT_BUF_EN 0
+#define CFG_IO_6_PD_DRV_STRG 10
+#define CFG_IO_6_PD_SLW_RT 1
+#define CFG_IO_6_PU_DRV_STRG 8
+#define CFG_IO_6_PU_SLW_RT 1
+#define CFG_IO_6_RTRIM 1
+#define CFG_IO_6_WK_PU_EN 0
+#define CFG_IO_7_INPUT_BUF_EN 1
+#define CFG_IO_7_PD_DRV_STRG 10
+#define CFG_IO_7_PD_SLW_RT 1
+#define CFG_IO_7_PU_DRV_STRG 8
+#define CFG_IO_7_PU_SLW_RT 1
+#define CFG_IO_7_RTRIM 1
+#define CFG_IO_7_WK_PU_EN 0
+#define CFG_IO_8_INPUT_BUF_EN 1
+#define CFG_IO_8_PD_DRV_STRG 10
+#define CFG_IO_8_PD_SLW_RT 1
+#define CFG_IO_8_PU_DRV_STRG 8
+#define CFG_IO_8_PU_SLW_RT 1
+#define CFG_IO_8_RTRIM 1
+#define CFG_IO_8_WK_PU_EN 0
+#define CFG_IO_9_INPUT_BUF_EN 1
+#define CFG_IO_9_PD_DRV_STRG 10
+#define CFG_IO_9_PD_SLW_RT 1
+#define CFG_IO_9_PU_DRV_STRG 8
+#define CFG_IO_9_PU_SLW_RT 1
+#define CFG_IO_9_RTRIM 1
+#define CFG_IO_9_WK_PU_EN 0
+#define CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
+#define CFG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
+#define PINMUX_DEDICATED_IO_10_SEL 10
+#define PINMUX_DEDICATED_IO_11_SEL 10
+#define PINMUX_DEDICATED_IO_12_SEL 10
+#define PINMUX_DEDICATED_IO_13_SEL 10
+#define PINMUX_DEDICATED_IO_14_SEL 10
+#define PINMUX_DEDICATED_IO_15_SEL 10
+#define PINMUX_DEDICATED_IO_16_SEL 13
+#define PINMUX_DEDICATED_IO_17_SEL 13
+#define PINMUX_DEDICATED_IO_4_SEL 4
+#define PINMUX_DEDICATED_IO_5_SEL 4
+#define PINMUX_DEDICATED_IO_6_SEL 4
+#define PINMUX_DEDICATED_IO_7_SEL 4
+#define PINMUX_DEDICATED_IO_8_SEL 4
+#define PINMUX_DEDICATED_IO_9_SEL 4
+#define PINMUX_I2C0_USEFPGA_SEL 0
+#define PINMUX_I2C1_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC0_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC1_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC2_USEFPGA_SEL 0
+#define PINMUX_NAND_USEFPGA_SEL 0
+#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0
+#define PINMUX_QSPI_USEFPGA_SEL 0
+#define PINMUX_RGMII0_USEFPGA_SEL 0
+#define PINMUX_RGMII1_USEFPGA_SEL 0
+#define PINMUX_RGMII2_USEFPGA_SEL 0
+#define PINMUX_SDMMC_USEFPGA_SEL 0
+#define PINMUX_SHARED_IO_Q1_10_SEL 8
+#define PINMUX_SHARED_IO_Q1_11_SEL 8
+#define PINMUX_SHARED_IO_Q1_12_SEL 8
+#define PINMUX_SHARED_IO_Q1_1_SEL 8
+#define PINMUX_SHARED_IO_Q1_2_SEL 8
+#define PINMUX_SHARED_IO_Q1_3_SEL 8
+#define PINMUX_SHARED_IO_Q1_4_SEL 8
+#define PINMUX_SHARED_IO_Q1_5_SEL 8
+#define PINMUX_SHARED_IO_Q1_6_SEL 8
+#define PINMUX_SHARED_IO_Q1_7_SEL 8
+#define PINMUX_SHARED_IO_Q1_8_SEL 8
+#define PINMUX_SHARED_IO_Q1_9_SEL 8
+#define PINMUX_SHARED_IO_Q2_10_SEL 4
+#define PINMUX_SHARED_IO_Q2_11_SEL 4
+#define PINMUX_SHARED_IO_Q2_12_SEL 4
+#define PINMUX_SHARED_IO_Q2_1_SEL 4
+#define PINMUX_SHARED_IO_Q2_2_SEL 4
+#define PINMUX_SHARED_IO_Q2_3_SEL 4
+#define PINMUX_SHARED_IO_Q2_4_SEL 4
+#define PINMUX_SHARED_IO_Q2_5_SEL 4
+#define PINMUX_SHARED_IO_Q2_6_SEL 4
+#define PINMUX_SHARED_IO_Q2_7_SEL 4
+#define PINMUX_SHARED_IO_Q2_8_SEL 4
+#define PINMUX_SHARED_IO_Q2_9_SEL 4
+#define PINMUX_SHARED_IO_Q3_10_SEL 10
+#define PINMUX_SHARED_IO_Q3_11_SEL 1
+#define PINMUX_SHARED_IO_Q3_12_SEL 1
+#define PINMUX_SHARED_IO_Q3_1_SEL 3
+#define PINMUX_SHARED_IO_Q3_2_SEL 3
+#define PINMUX_SHARED_IO_Q3_3_SEL 3
+#define PINMUX_SHARED_IO_Q3_4_SEL 3
+#define PINMUX_SHARED_IO_Q3_5_SEL 3
+#define PINMUX_SHARED_IO_Q3_6_SEL 15
+#define PINMUX_SHARED_IO_Q3_7_SEL 10
+#define PINMUX_SHARED_IO_Q3_8_SEL 10
+#define PINMUX_SHARED_IO_Q3_9_SEL 10
+#define PINMUX_SHARED_IO_Q4_10_SEL 12
+#define PINMUX_SHARED_IO_Q4_11_SEL 12
+#define PINMUX_SHARED_IO_Q4_12_SEL 12
+#define PINMUX_SHARED_IO_Q4_1_SEL 0
+#define PINMUX_SHARED_IO_Q4_2_SEL 0
+#define PINMUX_SHARED_IO_Q4_3_SEL 15
+#define PINMUX_SHARED_IO_Q4_4_SEL 12
+#define PINMUX_SHARED_IO_Q4_5_SEL 15
+#define PINMUX_SHARED_IO_Q4_6_SEL 15
+#define PINMUX_SHARED_IO_Q4_7_SEL 10
+#define PINMUX_SHARED_IO_Q4_8_SEL 15
+#define PINMUX_SHARED_IO_Q4_9_SEL 12
+#define PINMUX_SPIM0_USEFPGA_SEL 0
+#define PINMUX_SPIM1_USEFPGA_SEL 0
+#define PINMUX_SPIS0_USEFPGA_SEL 0
+#define PINMUX_SPIS1_USEFPGA_SEL 0
+#define PINMUX_UART0_USEFPGA_SEL 0
+#define PINMUX_UART1_USEFPGA_SEL 0
+#define PINMUX_USB0_USEFPGA_SEL 0
+#define PINMUX_USB1_USEFPGA_SEL 0
+
+/* Bridge Configuration */
+#define F2H_AXI_SLAVE 1
+#define F2SDRAM0_AXI_SLAVE 1
+#define F2SDRAM1_AXI_SLAVE 0
+#define F2SDRAM2_AXI_SLAVE 1
+#define H2F_AXI_MASTER 1
+#define LWH2F_AXI_MASTER 1
+
+/* Voltage Select for CFG IO */
+#define CFG_IO_BANK_VSEL \
+ (((CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
+ (CFG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
+
+/* Macro for CFG IO bit mapping */
+#define CFG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
+ ((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
+ ((NAME ## _WK_PU_EN & 0x1) << 16) | \
+ ((NAME ## _PU_SLW_RT & 0x1) << 13) | \
+ ((NAME ## _PU_DRV_STRG & 0xf) << 8) | \
+ ((NAME ## _PD_SLW_RT & 0x1) << 5) | \
+ (NAME ## _PD_DRV_STRG & 0x1f))
+
+#endif /* __SOCFPGA_ARRIA10_CFG_H__ */
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h
index 4e3fe305787..56f7c648207 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h
@@ -1,10 +1,10 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
- * Intel Arria 10 SoCFPGA configuration
+ * Altera Arria 10 SoCFPGA configuration
*/
-#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
-#define __SOCFPGA_ARRIA10_CONFIG_H__
+#ifndef __SOCFPGA_ARRIA10_CFG_H__
+#define __SOCFPGA_ARRIA10_CFG_H__
/* Clocks */
#define CB_INTOSC_LS_CLK_HZ 60000000
@@ -76,127 +76,127 @@
(ALTERAGRP_NOCCLK_MAINCNT))
/* Pin Mux Configuration */
-#define CONFIG_IO_10_INPUT_BUF_EN 0
-#define CONFIG_IO_10_PD_DRV_STRG 0
-#define CONFIG_IO_10_PD_SLW_RT 0
-#define CONFIG_IO_10_PU_DRV_STRG 0
-#define CONFIG_IO_10_PU_SLW_RT 0
-#define CONFIG_IO_10_RTRIM 1
-#define CONFIG_IO_10_WK_PU_EN 1
-#define CONFIG_IO_11_INPUT_BUF_EN 0
-#define CONFIG_IO_11_PD_DRV_STRG 0
-#define CONFIG_IO_11_PD_SLW_RT 0
-#define CONFIG_IO_11_PU_DRV_STRG 0
-#define CONFIG_IO_11_PU_SLW_RT 0
-#define CONFIG_IO_11_RTRIM 1
-#define CONFIG_IO_11_WK_PU_EN 1
-#define CONFIG_IO_12_INPUT_BUF_EN 1
-#define CONFIG_IO_12_PD_DRV_STRG 10
-#define CONFIG_IO_12_PD_SLW_RT 1
-#define CONFIG_IO_12_PU_DRV_STRG 8
-#define CONFIG_IO_12_PU_SLW_RT 1
-#define CONFIG_IO_12_RTRIM 1
-#define CONFIG_IO_12_WK_PU_EN 1
-#define CONFIG_IO_13_INPUT_BUF_EN 1
-#define CONFIG_IO_13_PD_DRV_STRG 10
-#define CONFIG_IO_13_PD_SLW_RT 1
-#define CONFIG_IO_13_PU_DRV_STRG 8
-#define CONFIG_IO_13_PU_SLW_RT 1
-#define CONFIG_IO_13_RTRIM 1
-#define CONFIG_IO_13_WK_PU_EN 1
-#define CONFIG_IO_14_INPUT_BUF_EN 1
-#define CONFIG_IO_14_PD_DRV_STRG 10
-#define CONFIG_IO_14_PD_SLW_RT 1
-#define CONFIG_IO_14_PU_DRV_STRG 8
-#define CONFIG_IO_14_PU_SLW_RT 1
-#define CONFIG_IO_14_RTRIM 1
-#define CONFIG_IO_14_WK_PU_EN 1
-#define CONFIG_IO_15_INPUT_BUF_EN 1
-#define CONFIG_IO_15_PD_DRV_STRG 10
-#define CONFIG_IO_15_PD_SLW_RT 1
-#define CONFIG_IO_15_PU_DRV_STRG 8
-#define CONFIG_IO_15_PU_SLW_RT 1
-#define CONFIG_IO_15_RTRIM 1
-#define CONFIG_IO_15_WK_PU_EN 1
-#define CONFIG_IO_16_INPUT_BUF_EN 0
-#define CONFIG_IO_16_PD_DRV_STRG 10
-#define CONFIG_IO_16_PD_SLW_RT 1
-#define CONFIG_IO_16_PU_DRV_STRG 8
-#define CONFIG_IO_16_PU_SLW_RT 1
-#define CONFIG_IO_16_RTRIM 1
-#define CONFIG_IO_16_WK_PU_EN 0
-#define CONFIG_IO_17_INPUT_BUF_EN 1
-#define CONFIG_IO_17_PD_DRV_STRG 10
-#define CONFIG_IO_17_PD_SLW_RT 1
-#define CONFIG_IO_17_PU_DRV_STRG 8
-#define CONFIG_IO_17_PU_SLW_RT 1
-#define CONFIG_IO_17_RTRIM 1
-#define CONFIG_IO_17_WK_PU_EN 0
-#define CONFIG_IO_1_INPUT_BUF_EN 1
-#define CONFIG_IO_1_PD_DRV_STRG 10
-#define CONFIG_IO_1_PD_SLW_RT 0
-#define CONFIG_IO_1_PU_DRV_STRG 8
-#define CONFIG_IO_1_PU_SLW_RT 0
-#define CONFIG_IO_1_RTRIM 1
-#define CONFIG_IO_1_WK_PU_EN 1
-#define CONFIG_IO_2_INPUT_BUF_EN 1
-#define CONFIG_IO_2_PD_DRV_STRG 10
-#define CONFIG_IO_2_PD_SLW_RT 0
-#define CONFIG_IO_2_PU_DRV_STRG 8
-#define CONFIG_IO_2_PU_SLW_RT 0
-#define CONFIG_IO_2_RTRIM 1
-#define CONFIG_IO_2_WK_PU_EN 1
-#define CONFIG_IO_3_INPUT_BUF_EN 1
-#define CONFIG_IO_3_PD_DRV_STRG 10
-#define CONFIG_IO_3_PD_SLW_RT 0
-#define CONFIG_IO_3_PU_DRV_STRG 8
-#define CONFIG_IO_3_PU_SLW_RT 0
-#define CONFIG_IO_3_RTRIM 1
-#define CONFIG_IO_3_WK_PU_EN 1
-#define CONFIG_IO_4_INPUT_BUF_EN 1
-#define CONFIG_IO_4_PD_DRV_STRG 10
-#define CONFIG_IO_4_PD_SLW_RT 1
-#define CONFIG_IO_4_PU_DRV_STRG 8
-#define CONFIG_IO_4_PU_SLW_RT 1
-#define CONFIG_IO_4_RTRIM 1
-#define CONFIG_IO_4_WK_PU_EN 0
-#define CONFIG_IO_5_INPUT_BUF_EN 1
-#define CONFIG_IO_5_PD_DRV_STRG 10
-#define CONFIG_IO_5_PD_SLW_RT 1
-#define CONFIG_IO_5_PU_DRV_STRG 8
-#define CONFIG_IO_5_PU_SLW_RT 1
-#define CONFIG_IO_5_RTRIM 1
-#define CONFIG_IO_5_WK_PU_EN 0
-#define CONFIG_IO_6_INPUT_BUF_EN 0
-#define CONFIG_IO_6_PD_DRV_STRG 10
-#define CONFIG_IO_6_PD_SLW_RT 1
-#define CONFIG_IO_6_PU_DRV_STRG 8
-#define CONFIG_IO_6_PU_SLW_RT 1
-#define CONFIG_IO_6_RTRIM 1
-#define CONFIG_IO_6_WK_PU_EN 0
-#define CONFIG_IO_7_INPUT_BUF_EN 1
-#define CONFIG_IO_7_PD_DRV_STRG 10
-#define CONFIG_IO_7_PD_SLW_RT 1
-#define CONFIG_IO_7_PU_DRV_STRG 8
-#define CONFIG_IO_7_PU_SLW_RT 1
-#define CONFIG_IO_7_RTRIM 1
-#define CONFIG_IO_7_WK_PU_EN 0
-#define CONFIG_IO_8_INPUT_BUF_EN 1
-#define CONFIG_IO_8_PD_DRV_STRG 10
-#define CONFIG_IO_8_PD_SLW_RT 1
-#define CONFIG_IO_8_PU_DRV_STRG 8
-#define CONFIG_IO_8_PU_SLW_RT 1
-#define CONFIG_IO_8_RTRIM 1
-#define CONFIG_IO_8_WK_PU_EN 0
-#define CONFIG_IO_9_INPUT_BUF_EN 1
-#define CONFIG_IO_9_PD_DRV_STRG 10
-#define CONFIG_IO_9_PD_SLW_RT 1
-#define CONFIG_IO_9_PU_DRV_STRG 8
-#define CONFIG_IO_9_PU_SLW_RT 1
-#define CONFIG_IO_9_RTRIM 1
-#define CONFIG_IO_9_WK_PU_EN 0
-#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
-#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
+#define CFG_IO_10_INPUT_BUF_EN 0
+#define CFG_IO_10_PD_DRV_STRG 0
+#define CFG_IO_10_PD_SLW_RT 0
+#define CFG_IO_10_PU_DRV_STRG 0
+#define CFG_IO_10_PU_SLW_RT 0
+#define CFG_IO_10_RTRIM 1
+#define CFG_IO_10_WK_PU_EN 1
+#define CFG_IO_11_INPUT_BUF_EN 0
+#define CFG_IO_11_PD_DRV_STRG 0
+#define CFG_IO_11_PD_SLW_RT 0
+#define CFG_IO_11_PU_DRV_STRG 0
+#define CFG_IO_11_PU_SLW_RT 0
+#define CFG_IO_11_RTRIM 1
+#define CFG_IO_11_WK_PU_EN 1
+#define CFG_IO_12_INPUT_BUF_EN 1
+#define CFG_IO_12_PD_DRV_STRG 10
+#define CFG_IO_12_PD_SLW_RT 1
+#define CFG_IO_12_PU_DRV_STRG 8
+#define CFG_IO_12_PU_SLW_RT 1
+#define CFG_IO_12_RTRIM 1
+#define CFG_IO_12_WK_PU_EN 1
+#define CFG_IO_13_INPUT_BUF_EN 1
+#define CFG_IO_13_PD_DRV_STRG 10
+#define CFG_IO_13_PD_SLW_RT 1
+#define CFG_IO_13_PU_DRV_STRG 8
+#define CFG_IO_13_PU_SLW_RT 1
+#define CFG_IO_13_RTRIM 1
+#define CFG_IO_13_WK_PU_EN 1
+#define CFG_IO_14_INPUT_BUF_EN 1
+#define CFG_IO_14_PD_DRV_STRG 10
+#define CFG_IO_14_PD_SLW_RT 1
+#define CFG_IO_14_PU_DRV_STRG 8
+#define CFG_IO_14_PU_SLW_RT 1
+#define CFG_IO_14_RTRIM 1
+#define CFG_IO_14_WK_PU_EN 1
+#define CFG_IO_15_INPUT_BUF_EN 1
+#define CFG_IO_15_PD_DRV_STRG 10
+#define CFG_IO_15_PD_SLW_RT 1
+#define CFG_IO_15_PU_DRV_STRG 8
+#define CFG_IO_15_PU_SLW_RT 1
+#define CFG_IO_15_RTRIM 1
+#define CFG_IO_15_WK_PU_EN 1
+#define CFG_IO_16_INPUT_BUF_EN 0
+#define CFG_IO_16_PD_DRV_STRG 10
+#define CFG_IO_16_PD_SLW_RT 1
+#define CFG_IO_16_PU_DRV_STRG 8
+#define CFG_IO_16_PU_SLW_RT 1
+#define CFG_IO_16_RTRIM 1
+#define CFG_IO_16_WK_PU_EN 0
+#define CFG_IO_17_INPUT_BUF_EN 1
+#define CFG_IO_17_PD_DRV_STRG 10
+#define CFG_IO_17_PD_SLW_RT 1
+#define CFG_IO_17_PU_DRV_STRG 8
+#define CFG_IO_17_PU_SLW_RT 1
+#define CFG_IO_17_RTRIM 1
+#define CFG_IO_17_WK_PU_EN 0
+#define CFG_IO_1_INPUT_BUF_EN 1
+#define CFG_IO_1_PD_DRV_STRG 10
+#define CFG_IO_1_PD_SLW_RT 0
+#define CFG_IO_1_PU_DRV_STRG 8
+#define CFG_IO_1_PU_SLW_RT 0
+#define CFG_IO_1_RTRIM 1
+#define CFG_IO_1_WK_PU_EN 1
+#define CFG_IO_2_INPUT_BUF_EN 1
+#define CFG_IO_2_PD_DRV_STRG 10
+#define CFG_IO_2_PD_SLW_RT 0
+#define CFG_IO_2_PU_DRV_STRG 8
+#define CFG_IO_2_PU_SLW_RT 0
+#define CFG_IO_2_RTRIM 1
+#define CFG_IO_2_WK_PU_EN 1
+#define CFG_IO_3_INPUT_BUF_EN 1
+#define CFG_IO_3_PD_DRV_STRG 10
+#define CFG_IO_3_PD_SLW_RT 0
+#define CFG_IO_3_PU_DRV_STRG 8
+#define CFG_IO_3_PU_SLW_RT 0
+#define CFG_IO_3_RTRIM 1
+#define CFG_IO_3_WK_PU_EN 1
+#define CFG_IO_4_INPUT_BUF_EN 1
+#define CFG_IO_4_PD_DRV_STRG 10
+#define CFG_IO_4_PD_SLW_RT 1
+#define CFG_IO_4_PU_DRV_STRG 8
+#define CFG_IO_4_PU_SLW_RT 1
+#define CFG_IO_4_RTRIM 1
+#define CFG_IO_4_WK_PU_EN 0
+#define CFG_IO_5_INPUT_BUF_EN 1
+#define CFG_IO_5_PD_DRV_STRG 10
+#define CFG_IO_5_PD_SLW_RT 1
+#define CFG_IO_5_PU_DRV_STRG 8
+#define CFG_IO_5_PU_SLW_RT 1
+#define CFG_IO_5_RTRIM 1
+#define CFG_IO_5_WK_PU_EN 0
+#define CFG_IO_6_INPUT_BUF_EN 0
+#define CFG_IO_6_PD_DRV_STRG 10
+#define CFG_IO_6_PD_SLW_RT 1
+#define CFG_IO_6_PU_DRV_STRG 8
+#define CFG_IO_6_PU_SLW_RT 1
+#define CFG_IO_6_RTRIM 1
+#define CFG_IO_6_WK_PU_EN 0
+#define CFG_IO_7_INPUT_BUF_EN 1
+#define CFG_IO_7_PD_DRV_STRG 10
+#define CFG_IO_7_PD_SLW_RT 1
+#define CFG_IO_7_PU_DRV_STRG 8
+#define CFG_IO_7_PU_SLW_RT 1
+#define CFG_IO_7_RTRIM 1
+#define CFG_IO_7_WK_PU_EN 0
+#define CFG_IO_8_INPUT_BUF_EN 1
+#define CFG_IO_8_PD_DRV_STRG 10
+#define CFG_IO_8_PD_SLW_RT 1
+#define CFG_IO_8_PU_DRV_STRG 8
+#define CFG_IO_8_PU_SLW_RT 1
+#define CFG_IO_8_RTRIM 1
+#define CFG_IO_8_WK_PU_EN 0
+#define CFG_IO_9_INPUT_BUF_EN 1
+#define CFG_IO_9_PD_DRV_STRG 10
+#define CFG_IO_9_PD_SLW_RT 1
+#define CFG_IO_9_PU_DRV_STRG 8
+#define CFG_IO_9_PU_SLW_RT 1
+#define CFG_IO_9_RTRIM 1
+#define CFG_IO_9_WK_PU_EN 0
+#define CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1
+#define CFG_IO_BANK_VOLTAGE_SEL_PERI_IO 1
#define PINMUX_DEDICATED_IO_10_SEL 10
#define PINMUX_DEDICATED_IO_11_SEL 10
#define PINMUX_DEDICATED_IO_12_SEL 8
@@ -288,13 +288,13 @@
#define H2F_AXI_MASTER 1
#define LWH2F_AXI_MASTER 1
-/* Voltage Select for Config IO */
-#define CONFIG_IO_BANK_VSEL \
- (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
- (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
+/* Voltage Select for CFG IO */
+#define CFG_IO_BANK_VSEL \
+ (((CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \
+ (CFG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))
-/* Macro for Config IO bit mapping */
-#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
+/* Macro for CFG IO bit mapping */
+#define CFG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \
((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \
((NAME ## _WK_PU_EN & 0x1) << 16) | \
((NAME ## _PU_SLW_RT & 0x1) << 13) | \
@@ -302,4 +302,4 @@
((NAME ## _PD_SLW_RT & 0x1) << 5) | \
(NAME ## _PD_DRV_STRG & 0x1f))
-#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */
+#endif /* __SOCFPGA_ARRIA10_CFG_H__ */
diff --git a/arch/arm/mach-socfpga/qts-filter-a10.sh b/arch/arm/mach-socfpga/qts-filter-a10.sh
index ab16522add5..8819c2051a7 100755
--- a/arch/arm/mach-socfpga/qts-filter-a10.sh
+++ b/arch/arm/mach-socfpga/qts-filter-a10.sh
@@ -25,11 +25,11 @@ process_a10_hps_config() {
(cat << EOF
// SPDX-License-Identifier: BSD-3-Clause
/*
- * Intel Arria 10 SoCFPGA configuration
+ * Altera Arria 10 SoCFPGA configuration
*/
-#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
-#define __SOCFPGA_ARRIA10_CONFIG_H__
+#ifndef __SOCFPGA_ARRIA10_CFG_H__
+#define __SOCFPGA_ARRIA10_CFG_H__
EOF
@@ -84,7 +84,7 @@ EOF
sed 's/SHARED_3V_IO_GRP_//' |
sed 's/FPGA_INTERFACE_GRP_//' |
sed 's/DEDICATED_IO_GRP_//' |
- sed 's/CONFIGURATION_DEDICATED/CONFIG/' |
+ sed 's/CONFIGURATION_DEDICATED/CFG/' |
sort
echo
@@ -98,14 +98,14 @@ EOF
sort
echo
- echo "/* Voltage Select for Config IO */"
- echo "#define CONFIG_IO_BANK_VSEL \\"
- echo " (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \\"
- echo " (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))"
+ echo "/* Voltage Select for CFG IO */"
+ echo "#define CFG_IO_BANK_VSEL \\"
+ echo " (((CFG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \\"
+ echo " (CFG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))"
echo
- echo "/* Macro for Config IO bit mapping */"
- echo -n "#define CONFIG_IO_MACRO(NAME) "
+ echo "/* Macro for CFG IO bit mapping */"
+ echo -n "#define CFG_IO_MACRO(NAME) "
echo "(((NAME ## _RTRIM & 0xff) << 19) | \\"
echo " ((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \\"
echo " ((NAME ## _WK_PU_EN & 0x1) << 16) | \\"
@@ -116,7 +116,7 @@ EOF
cat << EOF
-#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */
+#endif /* __SOCFPGA_ARRIA10_CFG_H__ */
EOF
) > "${outfile}"
}
--
2.43.7
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