[PATCH 1/4] arch: arm: dts: Add RTC clock nodes for ZynqMP platform

[Michal Simek]

From: Harini T <harini.t at amd.com>

Add fixed RTC clock nodes at 32.768 kHz for ZynqMP. The RTC driver uses
this clock to calculate the calibration value, replacing the deprecated
calibration device tree property.

Signed-off-by: Harini T <harini.t at amd.com>
Signed-off-by: Michal Simek <michal.simek at amd.com>
---

 arch/arm/dts/zynqmp-clk-ccf.dtsi | 15 ++++++++++++++-
 arch/arm/dts/zynqmp.dtsi         |  1 -
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 482f432ba7f3..877962df2b36 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -3,7 +3,7 @@
  * Clock specification for Xilinx ZynqMP
  *
  * (C) Copyright 2017 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek at amd.com>
  */
@@ -49,6 +49,14 @@
 		clock-frequency = <27000000>;
 		clock-output-names = "aux_ref_clk";
 	};
+
+	rtc_clk: rtc-clk {
+		bootph-all;
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "rtc_clk";
+	};
 };
 
 &zynqmp_firmware {
@@ -302,3 +310,8 @@
 			  <&zynqmp_clk DP_AUDIO_REF>,
 			  <&zynqmp_clk DP_VIDEO_REF>;  /* rpll, rpll, vpll */
 };
+
+&rtc {
+	clocks = <&rtc_clk>;
+	clock-names = "rtc";
+};
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 13cfca666572..c225eb219f4c 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -1006,7 +1006,6 @@
 			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "alarm", "sec";
-			calibration = <0x7FFF>;
 		};
 
 		sata: ahci at fd0c0000 {
-- 
2.43.0