[PATCH v4 2/4] rockchip: rk3568: make the TSADC trigger a first global reset
Andreas Zdziarstek
andreas.zdziarstek at gmail.com
Mon Jun 29 21:23:34 CEST 2026
Same rationale as the watchdog: the default second global reset leaves
the SoC hung. Set the TSADC to the first global reset as well, so a
thermal shutdown reliably resets the whole SoC.
Signed-off-by: Andreas Zdziarstek <andreas.zdziarstek at gmail.com>
---
arch/arm/mach-rockchip/rk3568/rk3568.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
index 8bed529a5c1..5e6f79450db 100644
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -40,6 +40,7 @@
#define CRU_BASE 0xfdd20000
#define WDT_GLB_SRST_CTRL BIT(1)
+#define TSADC_GLB_SRST_CTRL BIT(0)
/* PMU_GRF_GPIO0D_IOMUX_L */
enum {
@@ -152,8 +153,9 @@ int arch_cpu_init(void)
writel((PMU_PD_VO_DWN_ENA << 16),
PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON);
- /* Make WDT trigger a first global reset */
- setbits_le32(&cru->glb_rst_con, WDT_GLB_SRST_CTRL);
+ /* Make WDT and TSADC trigger a first global reset */
+ setbits_le32(&cru->glb_rst_con,
+ WDT_GLB_SRST_CTRL | TSADC_GLB_SRST_CTRL);
#endif
return 0;
}
--
2.53.0
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