[PATCH 11/14] clk: mediatek: mt8516: convert to struct mtk_parent
David Lechner
dlechner at baylibre.com
Tue Mar 3 01:03:20 CET 2026
Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.
Signed-off-by: David Lechner <dlechner at baylibre.com>
---
drivers/clk/mediatek/clk-mt8516.c | 786 +++++++++++++++++++-------------------
1 file changed, 393 insertions(+), 393 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c
index dac4aad61ef..fe796f3f4a7 100644
--- a/drivers/clk/mediatek/clk-mt8516.c
+++ b/drivers/clk/mediatek/clk-mt8516.c
@@ -116,432 +116,432 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
FACTOR1(CLK_TOP_ETH_D2, CLK_TOP_ETH_SEL, 1, 2),
};
-static const int uart0_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_UNIVPLL_D24,
+static const struct mtk_parent uart0_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D24),
};
-static const int gfmux_emi1x_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_DMPLL,
-};
-
-static const int emi_ddrphy_parents[] = {
- CLK_TOP_GFMUX_EMI1X_SEL,
- CLK_TOP_GFMUX_EMI1X_SEL,
-};
-
-static const int ahb_infra_parents[] = {
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK26M,
- CLK_TOP_MAINPLL_D11,
- CLK_TOP_CLK_NULL,
- CLK_TOP_MAINPLL_D12,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_MAINPLL_D10,
-};
-
-static const int csw_mux_mfg_parents[] = {
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_UNIVPLL_D3,
- CLK_TOP_UNIVPLL_D2,
- CLK_TOP_CLK26M,
- CLK_TOP_MAINPLL_D4,
- CLK_TOP_UNIVPLL_D24,
- CLK_TOP_MMPLL380M,
-};
-
-static const int msdc0_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_UNIVPLL_D6,
- CLK_TOP_MAINPLL_D8,
- CLK_TOP_UNIVPLL_D8,
- CLK_TOP_MAINPLL_D16,
- CLK_TOP_MMPLL_200M,
- CLK_TOP_MAINPLL_D12,
- CLK_TOP_MMPLL_D2,
-};
-
-static const int pwm_mm_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_UNIVPLL_D12,
-};
-
-static const int uart1_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_UNIVPLL_D24,
-};
-
-static const int msdc1_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_UNIVPLL_D6,
- CLK_TOP_MAINPLL_D8,
- CLK_TOP_UNIVPLL_D8,
- CLK_TOP_MAINPLL_D16,
- CLK_TOP_MMPLL_200M,
- CLK_TOP_MAINPLL_D12,
- CLK_TOP_MMPLL_D2,
-};
-
-static const int spm_52m_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_UNIVPLL_D24,
-};
-
-static const int pmicspi_parents[] = {
- CLK_TOP_UNIVPLL_D20,
- CLK_TOP_USB_PHY48M,
- CLK_TOP_UNIVPLL_D16,
- CLK_TOP_CLK26M,
-};
-
-static const int qaxi_aud26m_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_AHB_INFRA_SEL,
-};
-
-static const int aud_intbus_parents[] = {
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK26M,
- CLK_TOP_MAINPLL_D22,
- CLK_TOP_CLK_NULL,
- CLK_TOP_MAINPLL_D11,
-};
-
-static const int nfi2x_pad_parents[] = {
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK26M,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_MAINPLL_D12,
- CLK_TOP_MAINPLL_D8,
- CLK_TOP_CLK_NULL,
- CLK_TOP_MAINPLL_D6,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_MAINPLL_D4,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_MAINPLL_D10,
- CLK_TOP_MAINPLL_D7,
- CLK_TOP_CLK_NULL,
- CLK_TOP_MAINPLL_D5
-};
-
-static const int nfi1x_pad_parents[] = {
- CLK_TOP_AHB_INFRA_SEL,
- CLK_TOP_NFI1X,
-};
-
-static const int mfg_mm_parents[] = {
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CSW_MUX_MFG_SEL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_MAINPLL_D3,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK_NULL,
- CLK_TOP_MAINPLL_D5,
- CLK_TOP_MAINPLL_D7,
- CLK_TOP_CLK_NULL,
- CLK_TOP_MAINPLL_D14
-};
-
-static const int ddrphycfg_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_MAINPLL_D16
-};
-
-static const int usb_78m_parents[] = {
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK26M,
- CLK_TOP_UNIVPLL_D16,
- CLK_TOP_CLK_NULL,
- CLK_TOP_MAINPLL_D20,
-};
-
-static const int spinor_parents[] = {
- CLK_TOP_CLK26M_D2,
- CLK_TOP_CLK26M,
- CLK_TOP_MAINPLL_D40,
- CLK_TOP_UNIVPLL_D24,
- CLK_TOP_UNIVPLL_D20,
- CLK_TOP_MAINPLL_D20,
- CLK_TOP_MAINPLL_D16,
- CLK_TOP_UNIVPLL_D12
-};
-
-static const int msdc2_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_UNIVPLL_D6,
- CLK_TOP_MAINPLL_D8,
- CLK_TOP_UNIVPLL_D8,
- CLK_TOP_MAINPLL_D16,
- CLK_TOP_MMPLL_200M,
- CLK_TOP_MAINPLL_D12,
- CLK_TOP_MMPLL_D2
-};
-
-static const int eth_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_MAINPLL_D40,
- CLK_TOP_UNIVPLL_D24,
- CLK_TOP_UNIVPLL_D20,
- CLK_TOP_MAINPLL_D20
-};
-
-static const int axi_mfg_in_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_MAINPLL_D11,
- CLK_TOP_UNIVPLL_D24,
- CLK_TOP_MMPLL380M,
-};
-
-static const int slow_mfg_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_UNIVPLL_D12,
- CLK_TOP_UNIVPLL_D24
+static const struct mtk_parent gfmux_emi1x_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_DMPLL),
+};
+
+static const struct mtk_parent emi_ddrphy_parents[] = {
+ TOP_PARENT(CLK_TOP_GFMUX_EMI1X_SEL),
+ TOP_PARENT(CLK_TOP_GFMUX_EMI1X_SEL),
+};
+
+static const struct mtk_parent ahb_infra_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_MAINPLL_D11),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_MAINPLL_D12),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_MAINPLL_D10),
+};
+
+static const struct mtk_parent csw_mux_mfg_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D3),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D2),
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_MAINPLL_D4),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D24),
+ TOP_PARENT(CLK_TOP_MMPLL380M),
+};
+
+static const struct mtk_parent msdc0_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D6),
+ TOP_PARENT(CLK_TOP_MAINPLL_D8),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D8),
+ TOP_PARENT(CLK_TOP_MAINPLL_D16),
+ TOP_PARENT(CLK_TOP_MMPLL_200M),
+ TOP_PARENT(CLK_TOP_MAINPLL_D12),
+ TOP_PARENT(CLK_TOP_MMPLL_D2),
+};
+
+static const struct mtk_parent pwm_mm_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D12),
+};
+
+static const struct mtk_parent uart1_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D24),
+};
+
+static const struct mtk_parent msdc1_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D6),
+ TOP_PARENT(CLK_TOP_MAINPLL_D8),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D8),
+ TOP_PARENT(CLK_TOP_MAINPLL_D16),
+ TOP_PARENT(CLK_TOP_MMPLL_200M),
+ TOP_PARENT(CLK_TOP_MAINPLL_D12),
+ TOP_PARENT(CLK_TOP_MMPLL_D2),
+};
+
+static const struct mtk_parent spm_52m_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D24),
+};
+
+static const struct mtk_parent pmicspi_parents[] = {
+ TOP_PARENT(CLK_TOP_UNIVPLL_D20),
+ TOP_PARENT(CLK_TOP_USB_PHY48M),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D16),
+ TOP_PARENT(CLK_TOP_CLK26M),
+};
+
+static const struct mtk_parent qaxi_aud26m_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_AHB_INFRA_SEL),
+};
+
+static const struct mtk_parent aud_intbus_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_MAINPLL_D22),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_MAINPLL_D11),
+};
+
+static const struct mtk_parent nfi2x_pad_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_MAINPLL_D12),
+ TOP_PARENT(CLK_TOP_MAINPLL_D8),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_MAINPLL_D6),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_MAINPLL_D4),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_MAINPLL_D10),
+ TOP_PARENT(CLK_TOP_MAINPLL_D7),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_MAINPLL_D5),
+};
+
+static const struct mtk_parent nfi1x_pad_parents[] = {
+ TOP_PARENT(CLK_TOP_AHB_INFRA_SEL),
+ TOP_PARENT(CLK_TOP_NFI1X),
+};
+
+static const struct mtk_parent mfg_mm_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CSW_MUX_MFG_SEL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_MAINPLL_D3),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_MAINPLL_D5),
+ TOP_PARENT(CLK_TOP_MAINPLL_D7),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_MAINPLL_D14),
+};
+
+static const struct mtk_parent ddrphycfg_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_MAINPLL_D16),
+};
+
+static const struct mtk_parent usb_78m_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D16),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_MAINPLL_D20),
+};
+
+static const struct mtk_parent spinor_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M_D2),
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_MAINPLL_D40),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D24),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D20),
+ TOP_PARENT(CLK_TOP_MAINPLL_D20),
+ TOP_PARENT(CLK_TOP_MAINPLL_D16),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D12),
+};
+
+static const struct mtk_parent msdc2_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D6),
+ TOP_PARENT(CLK_TOP_MAINPLL_D8),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D8),
+ TOP_PARENT(CLK_TOP_MAINPLL_D16),
+ TOP_PARENT(CLK_TOP_MMPLL_200M),
+ TOP_PARENT(CLK_TOP_MAINPLL_D12),
+ TOP_PARENT(CLK_TOP_MMPLL_D2),
+};
+
+static const struct mtk_parent eth_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_MAINPLL_D40),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D24),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D20),
+ TOP_PARENT(CLK_TOP_MAINPLL_D20),
+};
+
+static const struct mtk_parent axi_mfg_in_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_MAINPLL_D11),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D24),
+ TOP_PARENT(CLK_TOP_MMPLL380M),
+};
+
+static const struct mtk_parent slow_mfg_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D12),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D24),
};
-
-static const int aud1_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_APLL1
-};
-
-static const int aud2_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_APLL2
-};
-
-static const int aud_engen1_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_RG_APLL1_D2_EN,
- CLK_TOP_RG_APLL1_D4_EN,
- CLK_TOP_RG_APLL1_D8_EN
+
+static const struct mtk_parent aud1_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_APLL1),
+};
+
+static const struct mtk_parent aud2_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_APLL2),
+};
+
+static const struct mtk_parent aud_engen1_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_RG_APLL1_D2_EN),
+ TOP_PARENT(CLK_TOP_RG_APLL1_D4_EN),
+ TOP_PARENT(CLK_TOP_RG_APLL1_D8_EN),
};
-static const int aud_engen2_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_RG_APLL2_D2_EN,
- CLK_TOP_RG_APLL2_D4_EN,
- CLK_TOP_RG_APLL2_D8_EN
+static const struct mtk_parent aud_engen2_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_RG_APLL2_D2_EN),
+ TOP_PARENT(CLK_TOP_RG_APLL2_D4_EN),
+ TOP_PARENT(CLK_TOP_RG_APLL2_D8_EN),
};
-static const int i2c_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_UNIVPLL_D20,
- CLK_TOP_UNIVPLL_D16,
- CLK_TOP_UNIVPLL_D12
+static const struct mtk_parent i2c_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D20),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D16),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D12),
};
-static const int aud_i2s0_m_parents[] = {
- CLK_TOP_RG_AUD1,
- CLK_TOP_RG_AUD2
+static const struct mtk_parent aud_i2s0_m_parents[] = {
+ TOP_PARENT(CLK_TOP_RG_AUD1),
+ TOP_PARENT(CLK_TOP_RG_AUD2),
};
-static const int pwm_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_UNIVPLL_D12
+static const struct mtk_parent pwm_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D12),
};
-static const int spi_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_UNIVPLL_D12,
- CLK_TOP_UNIVPLL_D8,
- CLK_TOP_UNIVPLL_D6
+static const struct mtk_parent spi_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D12),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D8),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D6),
};
-static const int aud_spdifin_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_UNIVPLL_D2
+static const struct mtk_parent aud_spdifin_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D2),
};
-static const int uart2_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_UNIVPLL_D24
+static const struct mtk_parent uart2_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D24),
};
-static const int bsi_parents[] = {
- CLK_TOP_CLK26M,
- CLK_TOP_MAINPLL_D10,
- CLK_TOP_MAINPLL_D12,
- CLK_TOP_MAINPLL_D20
+static const struct mtk_parent bsi_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_MAINPLL_D10),
+ TOP_PARENT(CLK_TOP_MAINPLL_D12),
+ TOP_PARENT(CLK_TOP_MAINPLL_D20),
};
-static const int dbg_atclk_parents[] = {
- CLK_TOP_CLK_NULL,
- CLK_TOP_CLK26M,
- CLK_TOP_MAINPLL_D5,
- CLK_TOP_CLK_NULL,
- CLK_TOP_UNIVPLL_D5
+static const struct mtk_parent dbg_atclk_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CLK26M),
+ TOP_PARENT(CLK_TOP_MAINPLL_D5),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_UNIVPLL_D5),
};
-static const int csw_nfiecc_parents[] = {
- CLK_TOP_CLK_NULL,
- CLK_TOP_MAINPLL_D7,
- CLK_TOP_MAINPLL_D6,
- CLK_TOP_CLK_NULL,
- CLK_TOP_MAINPLL_D5
+static const struct mtk_parent csw_nfiecc_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_MAINPLL_D7),
+ TOP_PARENT(CLK_TOP_MAINPLL_D6),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_MAINPLL_D5),
};
-static const int nfiecc_parents[] = {
- CLK_TOP_CLK_NULL,
- CLK_TOP_NFI2X_PAD_SEL,
- CLK_TOP_MAINPLL_D4,
- CLK_TOP_CLK_NULL,
- CLK_TOP_CSW_NFIECC_SEL,
+static const struct mtk_parent nfiecc_parents[] = {
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_NFI2X_PAD_SEL),
+ TOP_PARENT(CLK_TOP_MAINPLL_D4),
+ TOP_PARENT(CLK_TOP_CLK_NULL),
+ TOP_PARENT(CLK_TOP_CSW_NFIECC_SEL),
};
static const struct mtk_composite top_muxes[] = {
/* CLK_MUX_SEL0 */
- MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
- MUX(CLK_TOP_GFMUX_EMI1X_SEL, gfmux_emi1x_parents, 0x000, 1, 1),
- MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1),
- MUX(CLK_TOP_AHB_INFRA_SEL, ahb_infra_parents, 0x000, 4, 4),
- MUX(CLK_TOP_CSW_MUX_MFG_SEL, csw_mux_mfg_parents, 0x000, 8, 3),
- MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0x000, 11, 3),
- MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1),
- MUX(CLK_TOP_UART1_SEL, uart1_parents, 0x000, 19, 1),
- MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 20, 3),
- MUX(CLK_TOP_SPM_52M_SEL, spm_52m_parents, 0x000, 23, 1),
- MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 24, 2),
- MUX(CLK_TOP_QAXI_AUD26M_SEL, qaxi_aud26m_parents, 0x000, 26, 1),
- MUX(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x000, 27, 3),
+ MUX_MIXED(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
+ MUX_MIXED(CLK_TOP_GFMUX_EMI1X_SEL, gfmux_emi1x_parents, 0x000, 1, 1),
+ MUX_MIXED(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1),
+ MUX_MIXED(CLK_TOP_AHB_INFRA_SEL, ahb_infra_parents, 0x000, 4, 4),
+ MUX_MIXED(CLK_TOP_CSW_MUX_MFG_SEL, csw_mux_mfg_parents, 0x000, 8, 3),
+ MUX_MIXED(CLK_TOP_MSDC0_SEL, msdc0_parents, 0x000, 11, 3),
+ MUX_MIXED(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1),
+ MUX_MIXED(CLK_TOP_UART1_SEL, uart1_parents, 0x000, 19, 1),
+ MUX_MIXED(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 20, 3),
+ MUX_MIXED(CLK_TOP_SPM_52M_SEL, spm_52m_parents, 0x000, 23, 1),
+ MUX_MIXED(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 24, 2),
+ MUX_MIXED(CLK_TOP_QAXI_AUD26M_SEL, qaxi_aud26m_parents, 0x000, 26, 1),
+ MUX_MIXED(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x000, 27, 3),
/* CLK_MUX_SEL1 */
- MUX(CLK_TOP_NFI2X_PAD_SEL, nfi2x_pad_parents, 0x004, 0, 7),
- MUX(CLK_TOP_NFI1X_PAD_SEL, nfi1x_pad_parents, 0x004, 7, 1),
- MUX(CLK_TOP_MFG_MM_SEL, mfg_mm_parents, 0x004, 8, 6),
- MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
- MUX(CLK_TOP_USB_78M_SEL, usb_78m_parents, 0x004, 20, 3),
+ MUX_MIXED(CLK_TOP_NFI2X_PAD_SEL, nfi2x_pad_parents, 0x004, 0, 7),
+ MUX_MIXED(CLK_TOP_NFI1X_PAD_SEL, nfi1x_pad_parents, 0x004, 7, 1),
+ MUX_MIXED(CLK_TOP_MFG_MM_SEL, mfg_mm_parents, 0x004, 8, 6),
+ MUX_MIXED(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
+ MUX_MIXED(CLK_TOP_USB_78M_SEL, usb_78m_parents, 0x004, 20, 3),
/* CLK_MUX_SEL8 */
- MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3),
- MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0x040, 3, 3),
- MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
- MUX(CLK_TOP_AXI_MFG_IN_SEL, axi_mfg_in_parents, 0x040, 18, 2),
- MUX(CLK_TOP_SLOW_MFG_SEL, slow_mfg_parents, 0x040, 20, 2),
- MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
- MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
- MUX(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x040, 24, 2),
- MUX(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x040, 26, 2),
- MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 2),
+ MUX_MIXED(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3),
+ MUX_MIXED(CLK_TOP_MSDC2_SEL, msdc2_parents, 0x040, 3, 3),
+ MUX_MIXED(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
+ MUX_MIXED(CLK_TOP_AXI_MFG_IN_SEL, axi_mfg_in_parents, 0x040, 18, 2),
+ MUX_MIXED(CLK_TOP_SLOW_MFG_SEL, slow_mfg_parents, 0x040, 20, 2),
+ MUX_MIXED(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
+ MUX_MIXED(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
+ MUX_MIXED(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x040, 24, 2),
+ MUX_MIXED(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x040, 26, 2),
+ MUX_MIXED(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 2),
/* CLK_MUX_SEL9 */
- MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1),
- MUX(CLK_TOP_AUD_I2S1_M_SEL, aud_i2s0_m_parents, 0x044, 13, 1),
- MUX(CLK_TOP_AUD_I2S2_M_SEL, aud_i2s0_m_parents, 0x044, 14, 1),
- MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1),
- MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1),
- MUX(CLK_TOP_AUD_I2S5_M_SEL, aud_i2s0_m_parents, 0x044, 17, 1),
- MUX(CLK_TOP_AUD_SPDIF_B_SEL, aud_i2s0_m_parents, 0x044, 18, 1),
+ MUX_MIXED(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1),
+ MUX_MIXED(CLK_TOP_AUD_I2S1_M_SEL, aud_i2s0_m_parents, 0x044, 13, 1),
+ MUX_MIXED(CLK_TOP_AUD_I2S2_M_SEL, aud_i2s0_m_parents, 0x044, 14, 1),
+ MUX_MIXED(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1),
+ MUX_MIXED(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1),
+ MUX_MIXED(CLK_TOP_AUD_I2S5_M_SEL, aud_i2s0_m_parents, 0x044, 17, 1),
+ MUX_MIXED(CLK_TOP_AUD_SPDIF_B_SEL, aud_i2s0_m_parents, 0x044, 18, 1),
/* CLK_MUX_SEL13 */
- MUX(CLK_TOP_PWM_SEL, pwm_parents, 0x07c, 0, 1),
- MUX(CLK_TOP_SPI_SEL, spi_parents, 0x07c, 1, 2),
- MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 3, 1),
- MUX(CLK_TOP_UART2_SEL, uart2_parents, 0x07c, 4, 1),
- MUX(CLK_TOP_BSI_SEL, bsi_parents, 0x07c, 5, 2),
- MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3),
- MUX(CLK_TOP_CSW_NFIECC_SEL, csw_nfiecc_parents, 0x07c, 10, 3),
- MUX(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x07c, 13, 3),
+ MUX_MIXED(CLK_TOP_PWM_SEL, pwm_parents, 0x07c, 0, 1),
+ MUX_MIXED(CLK_TOP_SPI_SEL, spi_parents, 0x07c, 1, 2),
+ MUX_MIXED(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 3, 1),
+ MUX_MIXED(CLK_TOP_UART2_SEL, uart2_parents, 0x07c, 4, 1),
+ MUX_MIXED(CLK_TOP_BSI_SEL, bsi_parents, 0x07c, 5, 2),
+ MUX_MIXED(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3),
+ MUX_MIXED(CLK_TOP_CSW_NFIECC_SEL, csw_nfiecc_parents, 0x07c, 10, 3),
+ MUX_MIXED(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x07c, 13, 3),
};
static const struct mtk_gate_regs top0_cg_regs = {
--
2.43.0
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