[PATCH v1] spi: designware: add support for bits-per-word DT binding

[Ng, Boon Khai]

Hi Conor, Tom,

>> Why would this be inappropraite for the Linux kernel, once the system is
>> fully supported in Linux is the first question to answer. Thanks.

As Conor mentioned, the bits_per_word setting is obtained from the 
controller and validated at runtime.

Additionally, bits_per_word can also be sourced from ACPI, as shown in 
the Linux SPI driver code

https://github.com/torvalds/linux/blob/af4e9ef3d78420feb8fe58cd9a1ab80c501b3c08/drivers/spi/spi.c#L2739C7-L2739C20

> in its spi_device struct. I don't know if u-boot has similar
> functionality in its code, but looking at dm_spi_slave_plat which I
> think is your version of spi_device, that information is not there.
> 
Currently, U-Boot only supports an hardcoded 8-bit bits_per_word 
configuration.

> Were this submitted to linux with the current explanation, the feedback
> would be to set bits_per_word in the driver for whatever this "chip"
> that's being talked about is, presumably that means setting it in some
> sort of clock driver given that it controls a PLL?
> 
No, this isn't required by Linux, as the PLL only needs to be configured 
during the initial stage. This commit is specifically necessary for 
supporting the Agilex Smart NIC board, and I'm currently preparing 
patches for upstream submission. More details on the chip can be found, 
https://www.microchip.com/en-us/product/zl30793

Below is the link to the Smart NIC board:
https://www.silicom-usa.com/pr/4g-5g-products/4g-5g-adapters/fpga-smartnic-n6010-intel-based/

Below is the link to the patches I am preparing for upstream submission:
https://github.com/altera-fpga/u-boot-socfpga/blob/socfpga_v2025.10/board/intel/agilex-n6010/plldata.c

-- 
 >