[PATCH v5 00/10] Add PCIe Boot support for TI J784S4 SoC

[Siddharth Vadapalli]

On 05/03/26 00:21, Tom Rini wrote:
> On Mon, Feb 16, 2026 at 03:58:28PM +0530, Siddharth Vadapalli wrote:
> 
>> Hello,
>>
>> This series adds PCIe endpoint boot support for the TI J784S4 SoC.
>> Series is based on commit
>> f9ffeec4bdc board: toradex: Make A53 get RAM size from DT in K3 boards
>> of the master branch of U-Boot.
>>
>> v4 of this series is at:
>> https://patchwork.ozlabs.org/project/uboot/cover/20251201110103.845413-1-h-salunke@ti.com/
>> Changes since v4:
>> - Addressed Udit's feedback:
>>    i) Patch 6 has been updated by limiting changes to disabling CONFIG_SPL_PCI_ENDPOINT
>>       and CONFIG_SPL_PHY (CONFIG_PCIE_CDNS_TI_EP, CONFIG_SPL_PHY_CADENCE_TORRENT and
>>       CONFIG_SPL_PHY_J721E_WIZ don't need to be disabled as pointed out by Udit).
>>    ii) Commit message of patch 8 has been updated to indicate that although PCIe Boot
>>        is supported in Hardware for J742S2 SoC, it is not yet enabled in Software.
>>    iii) Documentation in patch 10 has been updated with complete set of device-tree
>>         changes included and the C Program to transfer bootloaders has also been
>>         simplified and documented with the usage of appropriate variable names.
>>
>> PCIe Boot Logs (J784S4-EVM running Linux as Root-Complex transfers
>> bootloaders to another J784S4-EVM configured for PCIe Boot):
>> https://gist.github.com/Siddharth-Vadapalli-at-TI/2d157003818441fe79a139d0dec1058a
> 
> With current next this introduces a failure to build on j784s4_evm_a72.
It builds for me without any issues. I have checkout out to next:
c0ca147ac62 Merge tag 'u-boot-imx-next-20260228' of 
https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
and don't see any issues when building A72 SPL / U-Boot proper for J784S4.

Could you please share the build error that you are observing? Or is it a 
warning being treated as an error?

Regards,
Siddharth.