[PATCH 4/4] ddr: imx: Remove unnecessary macro argument
Philip Molloy
philip at philipmolloy.com
Fri Mar 6 09:58:43 CET 2026
From: Philip Molloy <philip.molloy at analog.com>
IP2APB_DDRPHY_IPS_BASE_ADDR() is always passed 0, which is then
multiplied by 0x2000000. Since that results in adding 0 to the base
address, remove 0x2000000 and the argument entirely. Instead use
DDR_PHY_BASE, which was already defined in imx9. Add the missing
definition to imx8m.
Signed-off-by: Philip Molloy <philip.molloy at analog.com>
---
arch/arm/include/asm/arch-imx8m/ddr.h | 8 ++++----
arch/arm/include/asm/arch-imx9/ddr.h | 6 ++----
drivers/ddr/imx/imx8m/ddr_init.c | 8 ++++----
drivers/ddr/imx/phy/ddrphy_utils.c | 14 +++++++-------
drivers/ddr/imx/phy/helper.c | 2 +-
5 files changed, 18 insertions(+), 20 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h
index 47086d6b9f1..63c3aa682aa 100644
--- a/arch/arm/include/asm/arch-imx8m/ddr.h
+++ b/arch/arm/include/asm/arch-imx8m/ddr.h
@@ -10,9 +10,9 @@
#include <asm/types.h>
#include <asm/arch/imx-regs.h>
+#define DDR_PHY_BASE 0x3c000000
#define DDRC_DDR_SS_GPR0 0x3d000000
#define DDRC_IPS_BASE_ADDR_0 0x3f400000
-#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000))
struct ddrc_freq {
u32 res0[8];
@@ -635,7 +635,7 @@ enum msg_response {
#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
-#define DDRPHY_CalBusy(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4 * 0x020097)
+#define DDRPHY_CalBusy (DDR_PHY_BASE + 4 * 0x020097)
#define DRC_PERF_MON_BASE_ADDR(X) (0x3d800000 + ((X) * 0x2000000))
#define DRC_PERF_MON_CNT0_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x0)
@@ -741,8 +741,8 @@ static inline void reg32setbit(unsigned long addr, u32 bit)
}
#define dwc_ddrphy_apb_wr(addr, data) \
- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr), data)
+ reg32_write(DDR_PHY_BASE + ddrphy_addr_remap(addr), data)
#define dwc_ddrphy_apb_rd(addr) \
- reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr))
+ reg32_read(DDR_PHY_BASE + ddrphy_addr_remap(addr))
#endif
diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h
index 6c2069b9707..b6090a20a4d 100644
--- a/arch/arm/include/asm/arch-imx9/ddr.h
+++ b/arch/arm/include/asm/arch-imx9/ddr.h
@@ -34,8 +34,6 @@
#define REG_SRC_DPHY_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x20)
#define REG_SRC_DPHY_SINGLE_RESET_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x24)
-#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (DDR_PHY_BASE + ((X) * 0x2000000))
-
/* PHY State */
enum pstate {
PS0,
@@ -136,8 +134,8 @@ static inline void reg32setbit(unsigned long addr, u32 bit)
}
#define dwc_ddrphy_apb_wr(addr, data) \
- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr), data)
+ reg32_write(DDR_PHY_BASE + ddrphy_addr_remap(addr), data)
#define dwc_ddrphy_apb_rd(addr) \
- reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr))
+ reg32_read(DDR_PHY_BASE + ddrphy_addr_remap(addr))
#endif
diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c
index e9209ce8b61..39434334205 100644
--- a/drivers/ddr/imx/imx8m/ddr_init.c
+++ b/drivers/ddr/imx/imx8m/ddr_init.c
@@ -168,13 +168,13 @@ void get_trained_CDD(u32 fsp)
ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
if (ddr_type == 0x20) {
for (i = 0; i < 6; i++) {
- tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54013 + i) * 4);
+ tmp = reg32_read(DDR_PHY_BASE + (0x54013 + i) * 4);
cdd_cha[i * 2] = tmp & 0xff;
cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff;
}
for (i = 0; i < 7; i++) {
- tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x5402c + i) * 4);
+ tmp = reg32_read(DDR_PHY_BASE + (0x5402c + i) * 4);
if (i == 0) {
cdd_cha[0] = (tmp >> 8) & 0xff;
} else if (i == 6) {
@@ -205,7 +205,7 @@ void get_trained_CDD(u32 fsp)
unsigned int ddr4_cdd[64];
for (i = 0; i < 29; i++) {
- tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54012 + i) * 4);
+ tmp = reg32_read(DDR_PHY_BASE + (0x54012 + i) * 4);
ddr4_cdd[i * 2] = tmp & 0xff;
ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff;
}
@@ -401,7 +401,7 @@ int ddr_init(struct dram_timing_info *dram_timing)
* calibrating. Wait Calibrating done.
*/
do {
- tmp = reg32_read(DDRPHY_CalBusy(0));
+ tmp = reg32_read(DDRPHY_CalBusy);
} while ((tmp & 0x1));
debug("DDRINFO:ddrphy calibration done\n");
diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c
index b406418840c..22cd091f6ee 100644
--- a/drivers/ddr/imx/phy/ddrphy_utils.c
+++ b/drivers/ddr/imx/phy/ddrphy_utils.c
@@ -15,7 +15,7 @@ static inline void poll_pmu_message_ready(void)
unsigned int reg;
do {
- reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004));
+ reg = reg32_read(DDR_PHY_BASE + ddrphy_addr_remap(0xd0004));
} while (reg & 0x1);
}
@@ -23,13 +23,13 @@ static inline void ack_pmu_message_receive(void)
{
unsigned int reg;
- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x0);
+ reg32_write(DDR_PHY_BASE + ddrphy_addr_remap(0xd0031), 0x0);
do {
- reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004));
+ reg = reg32_read(DDR_PHY_BASE + ddrphy_addr_remap(0xd0004));
} while (!(reg & 0x1));
- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x1);
+ reg32_write(DDR_PHY_BASE + ddrphy_addr_remap(0xd0031), 0x1);
}
static inline unsigned int get_mail(void)
@@ -38,7 +38,7 @@ static inline unsigned int get_mail(void)
poll_pmu_message_ready();
- reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032));
+ reg = reg32_read(DDR_PHY_BASE + ddrphy_addr_remap(0xd0032));
ack_pmu_message_receive();
@@ -51,9 +51,9 @@ static inline unsigned int get_stream_message(void)
poll_pmu_message_ready();
- reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032));
+ reg = reg32_read(DDR_PHY_BASE + ddrphy_addr_remap(0xd0032));
- reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0034));
+ reg2 = reg32_read(DDR_PHY_BASE + ddrphy_addr_remap(0xd0034));
reg2 = (reg2 << 16) | reg;
diff --git a/drivers/ddr/imx/phy/helper.c b/drivers/ddr/imx/phy/helper.c
index 7b590ef397b..080a6fa1c57 100644
--- a/drivers/ddr/imx/phy/helper.c
+++ b/drivers/ddr/imx/phy/helper.c
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define IMEM_OFFSET_ADDR 0x00050000
#define DMEM_OFFSET_ADDR 0x00054000
-#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
+#define DDR_TRAIN_CODE_BASE_ADDR DDR_PHY_BASE
binman_sym_declare(ulong, ddr_1d_imem_fw, image_pos);
binman_sym_declare(ulong, ddr_1d_imem_fw, size);
--
2.53.0
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