[PATCH] rockchip: rk3568: Include all addressable DRAM in memory map

[Jonas Karlman]

Rockchip RK356x supports up to 8 GiB DRAM, however U-Boot only includes
the initial 32-bit 0-4 GiB addressable range in its memory map,
something that matches gd->ram_top and current expected memory available
for use in U-Boot.

The vendor DRAM init blobs add following ddr_mem rk atags [1]:

  4 GiB: [0x0, 0xf0000000) and [0x1f0000000, 0x200000000)
  8 GiB: [0x0, 0x200000000)

Add the remaining 64-bit 4-8 GiB addressable range, that already is
reported to OS, to the U-Boot memory map to more correctly describe all
available and addressable DRAM of RK356x. While at it also add the
missing UL suffix to the PCIe address range for consistency.

[1] https://gist.github.com/Kwiboo/6d983693c79365b43c330eb3191cbace

Acked-by: Quentin Schulz <quentin.schulz at cherry.de>
Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
---
Changes in v2:
- Update commit message
- Collect a-b tag
---
 arch/arm/mach-rockchip/rk3568/rk3568.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
index c2b96902d2dd..2b1eafee37c9 100644
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -72,9 +72,15 @@ static struct mm_region rk3568_mem_map[] = {
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	}, {
-		.virt = 0x300000000,
-		.phys = 0x300000000,
-		.size = 0x0c0c00000,
+		.virt = 0x100000000UL,
+		.phys = 0x100000000UL,
+		.size = 0x100000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x300000000UL,
+		.phys = 0x300000000UL,
+		.size = 0x0c0c00000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-- 
2.53.0