[PATCH] clk: rockchip: rk3528: Add CLK_REF_USB3OTG support

[Jonas Karlman]

The CLK_REF_USB3OTG clock is used as reference clock for the DWC3 block.

Add simple support to get rate of CLK_REF_USB3OTG clock to fix reference
clock period configuration.

Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
---
This fixes the ref_clk issue on RK3528 that is also fixed by "usb: dwc3:
core: Use IS_ERR_VALUE() for ref_clk rate check" [1].
---
 drivers/clk/rockchip/clk_rk3528.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c
index d58557ff56de..e1a84b38ad87 100644
--- a/drivers/clk/rockchip/clk_rk3528.c
+++ b/drivers/clk/rockchip/clk_rk3528.c
@@ -1337,6 +1337,7 @@ static ulong rk3528_clk_get_rate(struct clk *clk)
 					     DPLL);
 		break;
 
+	case CLK_REF_USB3OTG:
 	case TCLK_EMMC:
 	case TCLK_WDT_NS:
 		rate = OSC_HZ;
@@ -1457,6 +1458,7 @@ static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)
 		priv->ppll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL],
 						      priv->cru, PPLL);
 		break;
+	case CLK_REF_USB3OTG:
 	case TCLK_EMMC:
 	case TCLK_WDT_NS:
 		return (rate == OSC_HZ) ? 0 : -EINVAL;
-- 
2.53.0