[PATCH v2 0/4] IO+DDR low power mode bugfixes for AM62P and AM62A

[Akashdeep Kaur]

This series provides bugfixes for IO+DDR low power mode on AM62P and AM62A
SoCs by adding DDR errata workaround and 32kHz clock restoration.

Background:
-----------
During IO + DDR low power mode, the system enters into low power with DDR 
in self-refresh. For proper resume operation, two critical aspects must be
handled:

1. DDR Retention Latch: AM62AX and AM62PX are affected by errata i2487
   where DDR retention mode transition may fail, leading to data 
   corruption. A workaround sequence must clear the retention latch on 
   every boot.

2. 32kHz Clock Source: The SoC requires an accurate 32kHz clock for
   timing-critical subsystems. Without restoring the 32kHz LFOSC early
   during resume, the system falls back to the 32K RC oscillator (±20%
   accuracy), which is insufficient for components like RTC that rely on
   accurate timekeeping.

Changes:
--------
Patch 1: Add DDR errata i2487 workaround sequence that clears the data
         retention latch on every boot and abort scenarios. This ensures
         successful IO+DDR LPM resume for AM62AX and AM62PX.

Patches 2-4: Enable 32kHz LFOSC during LPM resume for AM62P and AM62A SoCs.
         Add function declaration to common LPM header and call it during
         resume path for both SoCs. Conditionally enabled via
         CONFIG_TI_K3_BOARD_LFOSC for boards with external crystal
         oscillators.

Testing:
--------
Tested IO + DDR low power mode on AM62PX-SK

Dependencies:
-------------
This series depends on the IO+DDR base support series v9 by
Markus Schneider-Pargmann:
https://lore.kernel.org/u-boot/20260105-topic-am62-ioddr-v2025-04-rc1-v9-0-7e33f2c77dbf@baylibre.com/

Base commit: v2026.01-rc4 (0e0a198a68be)

Changes in v2:
--------------
- Combined DDR errata workaround and 32kHz LFOSC patches into single series
- Rebased on v2026.01-rc4 with IO+DDR v9 series applied
- Link to v1: https://lore.kernel.org/u-boot/20251211093232.3706673-1-a-kaur@ti.com/

Signed-off-by: Akashdeep Kaur <a-kaur at ti.com>

---

Akashdeep Kaur (4):
  ram: ti: k3-ddrss: Add workaround sequence for errata i2487
  mach-k3: am62xx-lpm: Add 32kHz LFOSC enable function declaration
  mach-k3: am62px: Enable 32kHz LFOSC during LPM resume
  mach-k3: am62ax: Enable 32kHz LFOSC during LPM resume

 arch/arm/mach-k3/am62ax/am62a7_init.c |  3 +
 arch/arm/mach-k3/am62px/am62p5_init.c |  3 +
 arch/arm/mach-k3/am62xx-lpm-common.h  |  1 +
 drivers/ram/k3-ddrss/k3-ddrss-lpm.c   | 80 +++++++++++++++++++++++++++
 drivers/ram/k3-ddrss/k3-ddrss-lpm.h   |  1 +
 drivers/ram/k3-ddrss/k3-ddrss.c       |  5 ++
 6 files changed, 93 insertions(+)

-- 
2.34.1