[PATCH 01/16] clk: mediatek: replace xtal2_rate with struct mtk_parent
David Lechner
dlechner at baylibre.com
Tue Mar 10 16:32:14 CET 2026
Replace the hard-coded xtal rate for PLL parents with struct mtk_parent.
This avoids declaring the same clock rate in multiple places and will
allow future drivers to use an arbitrary clock.
The variable is renamed to something that better indicate what the field
is actually used for.
Signed-off-by: David Lechner <dlechner at baylibre.com>
---
drivers/clk/mediatek/clk-mt7622.c | 12 +++++++++++-
drivers/clk/mediatek/clk-mt7623.c | 12 +++++++++++-
drivers/clk/mediatek/clk-mt7629.c | 16 ++++++++++++++--
drivers/clk/mediatek/clk-mt8183.c | 12 +++++++++++-
drivers/clk/mediatek/clk-mt8188.c | 2 +-
drivers/clk/mediatek/clk-mt8189.c | 4 +---
drivers/clk/mediatek/clk-mt8195.c | 2 +-
drivers/clk/mediatek/clk-mt8365.c | 2 +-
drivers/clk/mediatek/clk-mt8512.c | 12 +++++++++++-
drivers/clk/mediatek/clk-mt8516.c | 12 +++++++++++-
drivers/clk/mediatek/clk-mt8518.c | 12 +++++++++++-
drivers/clk/mediatek/clk-mtk.c | 33 +++++++++++++++++++++++++--------
drivers/clk/mediatek/clk-mtk.h | 2 +-
13 files changed, 110 insertions(+), 23 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index e9a3f8ef0ba..cb637981499 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -28,6 +28,14 @@
#define MCU_BUS_MSK GENMASK(10, 9)
#define MCU_BUS_SEL(x) ((x) << 9)
+enum {
+ CLK_PAD_CLK25M,
+};
+
+static const ulong ext_clock_rates[] = {
+ [CLK_PAD_CLK25M] = 25 * MHZ,
+};
+
/* apmixedsys */
#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
_pd_shift, _pcw_reg, _pcw_shift) { \
@@ -597,7 +605,9 @@ static const struct mtk_gate ssusb_cgs[] = {
};
static const struct mtk_clk_tree mt7622_apmixed_clk_tree = {
- .xtal2_rate = 25 * MHZ,
+ .pll_parent = EXT_PARENT(CLK_PAD_CLK25M),
+ .ext_clk_rates = ext_clock_rates,
+ .num_ext_clks = ARRAY_SIZE(ext_clock_rates),
.plls = apmixed_plls,
.gates_offs = CLK_APMIXED_MAIN_CORE_EN,
.gates = apmixed_cgs,
diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index 9e1522d4615..1c34bfbf596 100644
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -24,6 +24,14 @@
#define AXI_DIV_MSK GENMASK(4, 0)
#define AXI_DIV_SEL(x) (x)
+enum {
+ CLK_PAD_CLK26M,
+};
+
+static const ulong ext_clock_rates[] = {
+ [CLK_PAD_CLK26M] = 26 * MHZ,
+};
+
/* apmixedsys */
static const int pll_id_offs_map[] = {
[0 ... CLK_APMIXED_NR - 1] = -1,
@@ -994,7 +1002,9 @@ static const struct mtk_gate hif_cgs[] = {
};
static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = {
- .xtal2_rate = 26 * MHZ,
+ .pll_parent = EXT_PARENT(CLK_PAD_CLK26M),
+ .ext_clk_rates = ext_clock_rates,
+ .num_ext_clks = ARRAY_SIZE(ext_clock_rates),
.id_offs_map = pll_id_offs_map,
.id_offs_map_size = ARRAY_SIZE(pll_id_offs_map),
.plls = apmixed_plls,
diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
index 42670269d3e..beba7fc4abc 100644
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -28,6 +28,14 @@
#define MCU_BUS_MSK GENMASK(10, 9)
#define MCU_BUS_SEL(x) ((x) << 9)
+enum {
+ CLK_PAD_CLK20M,
+};
+
+static const ulong ext_clock_rates[] = {
+ [CLK_PAD_CLK20M] = 20 * MHZ,
+};
+
/* apmixedsys */
#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
_pd_shift, _pcw_reg, _pcw_shift) { \
@@ -567,7 +575,9 @@ static const struct mtk_gate ssusb_cgs[] = {
static const struct mtk_clk_tree mt7629_clk_tree = {
.xtal_rate = 40 * MHZ,
- .xtal2_rate = 20 * MHZ,
+ .pll_parent = EXT_PARENT(CLK_PAD_CLK20M),
+ .ext_clk_rates = ext_clock_rates,
+ .num_ext_clks = ARRAY_SIZE(ext_clock_rates),
.fdivs_offs = CLK_TOP_TO_USB3_SYS,
.muxes_offs = CLK_TOP_AXI_SEL,
.plls = apmixed_plls,
@@ -582,7 +592,9 @@ static const struct mtk_clk_tree mt7629_clk_tree = {
static const struct mtk_clk_tree mt7629_peri_clk_tree = {
.xtal_rate = 40 * MHZ,
- .xtal2_rate = 20 * MHZ,
+ .pll_parent = EXT_PARENT(CLK_PAD_CLK20M),
+ .ext_clk_rates = ext_clock_rates,
+ .num_ext_clks = ARRAY_SIZE(ext_clock_rates),
.fdivs_offs = CLK_TOP_TO_USB3_SYS,
.muxes_offs = CLK_TOP_AXI_SEL,
.plls = apmixed_plls,
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 54e31efd2ea..6158441fb95 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -17,6 +17,14 @@
#define MT8183_PLL_FMAX (3800UL * MHZ)
#define MT8183_PLL_FMIN (1500UL * MHZ)
+enum {
+ CLK_PAD_CLK26M,
+};
+
+static const ulong ext_clock_rates[] = {
+ [CLK_PAD_CLK26M] = 26 * MHZ,
+};
+
/* apmixedsys */
#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, \
_pcwibits, _pd_reg, _pd_shift, _pcw_reg, _pcw_shift) { \
@@ -598,7 +606,9 @@ static const struct mtk_composite top_muxes[] = {
static const struct mtk_clk_tree mt8183_clk_tree = {
.xtal_rate = 26 * MHZ,
- .xtal2_rate = 26 * MHZ,
+ .pll_parent = EXT_PARENT(CLK_PAD_CLK26M),
+ .ext_clk_rates = ext_clock_rates,
+ .num_ext_clks = ARRAY_SIZE(ext_clock_rates),
.fdivs_offs = CLK_TOP_CLK13M,
.muxes_offs = CLK_TOP_MUX_AXI,
.plls = apmixed_plls,
diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c
index e4297c92bd9..ca5fa8af86e 100644
--- a/drivers/clk/mediatek/clk-mt8188.c
+++ b/drivers/clk/mediatek/clk-mt8188.c
@@ -85,7 +85,7 @@ static const struct mtk_pll_data apmixed_plls[] = {
static const struct mtk_clk_tree mt8188_apmixedsys_clk_tree = {
.xtal_rate = 26 * MHZ,
- .xtal2_rate = 26 * MHZ,
+ .pll_parent = EXT_PARENT(CLK_PAD_CLK26M),
.ext_clk_rates = ext_clock_rates,
.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
.plls = apmixed_plls,
diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c
index bce54c9a45f..1f75d873516 100644
--- a/drivers/clk/mediatek/clk-mt8189.c
+++ b/drivers/clk/mediatek/clk-mt8189.c
@@ -1636,8 +1636,7 @@ static const struct mtk_gate mminfra_config_clks[] = {
};
static const struct mtk_clk_tree mt8189_apmixedsys_clk_tree = {
- .xtal_rate = 26 * MHZ,
- .xtal2_rate = 26 * MHZ,
+ .pll_parent = EXT_PARENT(CLK_PAD_CLK26M),
.ext_clk_rates = pad_clks,
.num_ext_clks = ARRAY_SIZE(pad_clks),
.plls = apmixed_plls,
@@ -1645,7 +1644,6 @@ static const struct mtk_clk_tree mt8189_apmixedsys_clk_tree = {
};
static const struct mtk_clk_tree mt8189_topckgen_clk_tree = {
- .xtal_rate = 26 * MHZ,
.ext_clk_rates = pad_clks,
.num_ext_clks = ARRAY_SIZE(pad_clks),
.fdivs_offs = CLK_TOP_MAINPLL_D3,
diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c
index 76ece913187..28b2e2f12ac 100644
--- a/drivers/clk/mediatek/clk-mt8195.c
+++ b/drivers/clk/mediatek/clk-mt8195.c
@@ -97,7 +97,7 @@ static const struct mtk_pll_data apmixed_plls[] = {
static const struct mtk_clk_tree mt8195_apmixedsys_clk_tree = {
.xtal_rate = 26 * MHZ,
- .xtal2_rate = 26 * MHZ,
+ .pll_parent = EXT_PARENT(CLK_PAD_CLK26M),
.ext_clk_rates = ext_clock_rates,
.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
.plls = apmixed_plls,
diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c
index 16531491a0f..15df6422661 100644
--- a/drivers/clk/mediatek/clk-mt8365.c
+++ b/drivers/clk/mediatek/clk-mt8365.c
@@ -75,7 +75,7 @@ static const struct mtk_pll_data apmixed_plls[] = {
static const struct mtk_clk_tree mt8365_apmixed_tree = {
.xtal_rate = 26 * MHZ,
- .xtal2_rate = 26 * MHZ,
+ .pll_parent = EXT_PARENT(CLK_PAD_CLK26M),
.ext_clk_rates = ext_clk_rates,
.num_ext_clks = ARRAY_SIZE(ext_clk_rates),
.plls = apmixed_plls,
diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c
index de0d3eae7ee..f7d41f4cfdb 100644
--- a/drivers/clk/mediatek/clk-mt8512.c
+++ b/drivers/clk/mediatek/clk-mt8512.c
@@ -17,6 +17,14 @@
#define MT8512_PLL_FMIN (1500UL * MHZ)
#define MT8512_CON0_RST_BAR BIT(23)
+enum {
+ CLK_PAD_CLK26M,
+};
+
+static const ulong ext_clock_rates[] = {
+ [CLK_PAD_CLK26M] = 26 * MHZ,
+};
+
/* apmixedsys */
#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
_pd_shift, _pcw_reg, _pcw_shift, _pcw_chg_reg) { \
@@ -786,7 +794,9 @@ static const struct mtk_gate infra_clks[] = {
static const struct mtk_clk_tree mt8512_clk_tree = {
.xtal_rate = 26 * MHZ,
- .xtal2_rate = 26 * MHZ,
+ .pll_parent = EXT_PARENT(CLK_PAD_CLK26M),
+ .ext_clk_rates = ext_clock_rates,
+ .num_ext_clks = ARRAY_SIZE(ext_clock_rates),
.fdivs_offs = CLK_TOP_SYSPLL1_D2,
.muxes_offs = CLK_TOP_AXI_SEL,
.plls = apmixed_plls,
diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c
index 6b30ea9ce4a..74966051b1c 100644
--- a/drivers/clk/mediatek/clk-mt8516.c
+++ b/drivers/clk/mediatek/clk-mt8516.c
@@ -16,6 +16,14 @@
#define MT8516_PLL_FMAX (1502UL * MHZ)
#define MT8516_CON0_RST_BAR BIT(27)
+enum {
+ CLK_PAD_CLK26M,
+};
+
+static const ulong ext_clock_rates[] = {
+ [CLK_PAD_CLK26M] = 26 * MHZ,
+};
+
/* apmixedsys */
#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
_pd_shift, _pcw_reg, _pcw_shift) { \
@@ -738,7 +746,9 @@ static const struct mtk_gate top_clks[] = {
static const struct mtk_clk_tree mt8516_clk_tree = {
.xtal_rate = 26 * MHZ,
- .xtal2_rate = 26 * MHZ,
+ .pll_parent = EXT_PARENT(CLK_PAD_CLK26M),
+ .ext_clk_rates = ext_clock_rates,
+ .num_ext_clks = ARRAY_SIZE(ext_clock_rates),
.fdivs_offs = CLK_TOP_DMPLL,
.muxes_offs = CLK_TOP_UART0_SEL,
.plls = apmixed_plls,
diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c
index 34fa5a127d5..85cbb35446b 100644
--- a/drivers/clk/mediatek/clk-mt8518.c
+++ b/drivers/clk/mediatek/clk-mt8518.c
@@ -16,6 +16,14 @@
#define MT8518_PLL_FMAX (3000UL * MHZ)
#define MT8518_CON0_RST_BAR BIT(27)
+enum {
+ CLK_PAD_CLK26M,
+};
+
+static const ulong ext_clock_rates[] = {
+ [CLK_PAD_CLK26M] = 26 * MHZ,
+};
+
/* apmixedsys */
#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
_pd_shift, _pcw_reg, _pcw_shift) { \
@@ -1494,7 +1502,9 @@ static const struct mtk_gate top_clks[] = {
static const struct mtk_clk_tree mt8518_clk_tree = {
.xtal_rate = 26 * MHZ,
- .xtal2_rate = 26 * MHZ,
+ .pll_parent = EXT_PARENT(CLK_PAD_CLK26M),
+ .ext_clk_rates = ext_clock_rates,
+ .num_ext_clks = ARRAY_SIZE(ext_clock_rates),
.fdivs_offs = CLK_TOP_DMPLL,
.muxes_offs = CLK_TOP_UART0_SEL,
.plls = apmixed_plls,
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index fa4a84bfceb..0b6eb0dbc04 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -499,16 +499,21 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_priv *priv, u32 id,
* @postdiv: The post divider (output)
* @freq: The desired target frequency
*/
-static void mtk_pll_calc_values(struct mtk_clk_priv *priv, u32 id,
- u32 *pcw, u32 *postdiv, u32 freq)
+static int mtk_pll_calc_values(struct mtk_clk_priv *priv, struct clk *clk,
+ u32 *pcw, u32 *postdiv, u32 freq)
{
const struct mtk_pll_data *pll;
- unsigned long fmin;
+ const struct mtk_parent *parent = &priv->tree->pll_parent;
+ unsigned long xtal_rate, fmin;
u64 _pcw;
int ibits;
u32 val;
- pll = &priv->tree->plls[id];
+ xtal_rate = mtk_find_parent_rate(priv, clk, parent->id, parent->flags);
+ if (IS_ERR_VALUE(xtal_rate))
+ return xtal_rate;
+
+ pll = &priv->tree->plls[clk->id];
fmin = pll->fmin ? pll->fmin : 1000 * MHZ;
if (freq > pll->fmax)
@@ -523,9 +528,11 @@ static void mtk_pll_calc_values(struct mtk_clk_priv *priv, u32 id,
/* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */
ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
_pcw = ((u64)freq << val) << (pll->pcwbits - ibits);
- do_div(_pcw, priv->tree->xtal2_rate);
+ do_div(_pcw, xtal_rate);
*pcw = (u32)_pcw;
+
+ return 0;
}
static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate)
@@ -533,11 +540,15 @@ static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate)
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
u32 pcw = 0;
u32 postdiv;
+ int ret;
if (!mtk_clk_id_is_pll(priv->tree, clk->id))
return -EINVAL;
- mtk_pll_calc_values(priv, clk->id, &pcw, &postdiv, rate);
+ ret = mtk_pll_calc_values(priv, clk, &pcw, &postdiv, rate);
+ if (ret)
+ return ret;
+
mtk_pll_set_rate_regs(priv, clk->id, pcw, postdiv);
return 0;
@@ -546,8 +557,10 @@ static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate)
static ulong mtk_apmixedsys_get_rate(struct clk *clk)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
+ const struct mtk_parent *parent;
const struct mtk_pll_data *pll;
const struct mtk_gate *gate;
+ unsigned long xtal_rate;
u32 postdiv;
u32 pcw;
@@ -557,6 +570,11 @@ static ulong mtk_apmixedsys_get_rate(struct clk *clk)
return mtk_find_parent_rate(priv, clk, gate->parent, gate->flags);
}
+ parent = &priv->tree->pll_parent;
+ xtal_rate = mtk_find_parent_rate(priv, clk, parent->id, parent->flags);
+ if (IS_ERR_VALUE(xtal_rate))
+ return xtal_rate;
+
pll = &priv->tree->plls[clk->id];
postdiv = (readl(priv->base + pll->pd_reg) >> pll->pd_shift) &
@@ -566,8 +584,7 @@ static ulong mtk_apmixedsys_get_rate(struct clk *clk)
pcw = readl(priv->base + pll->pcw_reg) >> pll->pcw_shift;
pcw &= GENMASK(pll->pcwbits - 1, 0);
- return __mtk_pll_recalc_rate(pll, priv->tree->xtal2_rate,
- pcw, postdiv);
+ return __mtk_pll_recalc_rate(pll, xtal_rate, pcw, postdiv);
}
static int mtk_apmixedsys_enable(struct clk *clk)
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 10a0723de47..682b4303585 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -234,7 +234,7 @@ struct mtk_gate {
/* struct mtk_clk_tree - clock tree */
struct mtk_clk_tree {
unsigned long xtal_rate;
- unsigned long xtal2_rate;
+ const struct mtk_parent pll_parent;
/* External fixed clocks - excluded from mapping. */
const ulong *ext_clk_rates;
const int num_ext_clks;
--
2.43.0
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