[PATCH 02/16] clk: mediatek: mt7622: convert CLK_XTAL to CLK_PAD_CLK25M
David Lechner
dlechner at baylibre.com
Tue Mar 10 16:32:15 CET 2026
Replace all uses of CLK_XTAL with CLK_PAD_CLK25M.
This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.
Signed-off-by: David Lechner <dlechner at baylibre.com>
---
drivers/clk/mediatek/clk-mt7622.c | 109 ++++++++++++++++++++------------------
1 file changed, 56 insertions(+), 53 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index cb637981499..cecf1d3b91a 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -94,7 +94,7 @@ static const struct mtk_gate apmixed_cgs[] = {
/* topckgen */
#define FIXED_CLK0(_id, _rate) \
- FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)
+ FIXED_CLK(_id, CLK_PAD_CLK25M, CLK_PARENT_EXT, _rate)
#define FACTOR0(_id, _parent, _mult, _div) \
FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
@@ -103,7 +103,7 @@ static const struct mtk_gate apmixed_cgs[] = {
FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
#define FACTOR2(_id, _parent, _mult, _div) \
- FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL)
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT)
static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK0(CLK_TOP_TO_U2_PHY, 31250000),
@@ -124,8 +124,8 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125),
FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1),
- FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024),
- FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1),
+ FACTOR2(CLK_TOP_RTC, CLK_PAD_CLK25M, 1, 1024),
+ FACTOR2(CLK_TOP_MEMPLL, CLK_PAD_CLK25M, 32, 1),
FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
@@ -168,7 +168,7 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
};
static const struct mtk_parent axi_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_SYSPLL1_D2),
TOP_PARENT(CLK_TOP_SYSPLL_D5),
TOP_PARENT(CLK_TOP_SYSPLL1_D4),
@@ -178,17 +178,17 @@ static const struct mtk_parent axi_parents[] = {
};
static const struct mtk_parent mem_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_DMPLL),
};
static const struct mtk_parent ddrphycfg_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_SYSPLL1_D8),
};
static const struct mtk_parent eth_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_SYSPLL1_D2),
TOP_PARENT(CLK_TOP_UNIVPLL1_D2),
TOP_PARENT(CLK_TOP_SYSPLL1_D4),
@@ -198,24 +198,24 @@ static const struct mtk_parent eth_parents[] = {
};
static const struct mtk_parent pwm_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_UNIVPLL2_D4),
};
static const struct mtk_parent f10m_ref_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_SYSPLL4_D16),
};
static const struct mtk_parent nfi_infra_parents[] = {
- XTAL_PARENT(CLK_XTAL),
- XTAL_PARENT(CLK_XTAL),
- XTAL_PARENT(CLK_XTAL),
- XTAL_PARENT(CLK_XTAL),
- XTAL_PARENT(CLK_XTAL),
- XTAL_PARENT(CLK_XTAL),
- XTAL_PARENT(CLK_XTAL),
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
+ EXT_PARENT(CLK_PAD_CLK25M),
+ EXT_PARENT(CLK_PAD_CLK25M),
+ EXT_PARENT(CLK_PAD_CLK25M),
+ EXT_PARENT(CLK_PAD_CLK25M),
+ EXT_PARENT(CLK_PAD_CLK25M),
+ EXT_PARENT(CLK_PAD_CLK25M),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_UNIVPLL2_D8),
TOP_PARENT(CLK_TOP_SYSPLL1_D8),
TOP_PARENT(CLK_TOP_UNIVPLL1_D8),
@@ -226,7 +226,7 @@ static const struct mtk_parent nfi_infra_parents[] = {
};
static const struct mtk_parent flash_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_UNIVPLL_D80_D4),
TOP_PARENT(CLK_TOP_SYSPLL2_D8),
TOP_PARENT(CLK_TOP_SYSPLL3_D4),
@@ -237,61 +237,61 @@ static const struct mtk_parent flash_parents[] = {
};
static const struct mtk_parent uart_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_UNIVPLL2_D8),
};
static const struct mtk_parent spi0_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_SYSPLL3_D2),
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_SYSPLL2_D4),
TOP_PARENT(CLK_TOP_SYSPLL4_D2),
TOP_PARENT(CLK_TOP_UNIVPLL2_D4),
TOP_PARENT(CLK_TOP_UNIVPLL1_D8),
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
};
static const struct mtk_parent spi1_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_SYSPLL3_D2),
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_SYSPLL4_D4),
TOP_PARENT(CLK_TOP_SYSPLL4_D2),
TOP_PARENT(CLK_TOP_UNIVPLL2_D4),
TOP_PARENT(CLK_TOP_UNIVPLL1_D8),
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
};
static const struct mtk_parent msdc30_0_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_UNIVPLL2_D16),
TOP_PARENT(CLK_TOP_UNIV48M),
};
static const struct mtk_parent a1sys_hp_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_AUD1PLL),
TOP_PARENT(CLK_TOP_AUD2PLL),
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
};
static const struct mtk_parent intdir_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_SYSPLL1_D2),
TOP_PARENT(CLK_TOP_UNIVPLL_D2),
TOP_PARENT(CLK_TOP_SGMIIPLL),
};
static const struct mtk_parent aud_intbus_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_SYSPLL1_D4),
TOP_PARENT(CLK_TOP_SYSPLL4_D2),
TOP_PARENT(CLK_TOP_SYSPLL3_D2),
};
static const struct mtk_parent pmicspi_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
VOID_PARENT,
VOID_PARENT,
VOID_PARENT,
@@ -300,32 +300,32 @@ static const struct mtk_parent pmicspi_parents[] = {
};
static const struct mtk_parent atb_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_SYSPLL1_D2),
TOP_PARENT(CLK_TOP_SYSPLL_D5),
};
static const struct mtk_parent audio_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_SYSPLL3_D4),
TOP_PARENT(CLK_TOP_SYSPLL4_D4),
TOP_PARENT(CLK_TOP_UNIVPLL1_D16),
};
static const struct mtk_parent usb20_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_UNIVPLL3_D4),
TOP_PARENT(CLK_TOP_SYSPLL1_D8),
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
};
static const struct mtk_parent aud1_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_AUD1PLL),
};
static const struct mtk_parent asm_l_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
TOP_PARENT(CLK_TOP_SYSPLL_D5),
TOP_PARENT(CLK_TOP_UNIVPLL2_D2),
TOP_PARENT(CLK_TOP_UNIVPLL2_D4),
@@ -396,7 +396,7 @@ static const struct mtk_composite top_muxes[] = {
/* infracfg */
static const struct mtk_parent infra_mux1_parents[] = {
- XTAL_PARENT(CLK_XTAL),
+ EXT_PARENT(CLK_PAD_CLK25M),
APMIXED_PARENT(CLK_APMIXED_MAINPLL),
APMIXED_PARENT(CLK_APMIXED_MAIN_CORE_EN),
APMIXED_PARENT(CLK_APMIXED_MAINPLL),
@@ -460,8 +460,8 @@ static const struct mtk_gate_regs peri1_cg_regs = {
}
#define GATE_PERI0(_id, _parent, _shift) \
GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
-#define GATE_PERI0_XTAL(_id, _parent, _shift) \
- GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL)
+#define GATE_PERI0_EXT(_id, _parent, _shift) \
+ GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_EXT)
#define GATE_PERI1(_id, _parent, _shift) { \
.id = _id, \
@@ -474,14 +474,14 @@ static const struct mtk_gate_regs peri1_cg_regs = {
static const struct mtk_gate peri_cgs[] = {
/* PERI0 */
GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1),
- GATE_PERI0_XTAL(CLK_PERI_PWM1_PD, CLK_XTAL, 2),
- GATE_PERI0_XTAL(CLK_PERI_PWM2_PD, CLK_XTAL, 3),
- GATE_PERI0_XTAL(CLK_PERI_PWM3_PD, CLK_XTAL, 4),
- GATE_PERI0_XTAL(CLK_PERI_PWM4_PD, CLK_XTAL, 5),
- GATE_PERI0_XTAL(CLK_PERI_PWM5_PD, CLK_XTAL, 6),
- GATE_PERI0_XTAL(CLK_PERI_PWM6_PD, CLK_XTAL, 7),
- GATE_PERI0_XTAL(CLK_PERI_PWM7_PD, CLK_XTAL, 8),
- GATE_PERI0_XTAL(CLK_PERI_PWM_PD, CLK_XTAL, 9),
+ GATE_PERI0_EXT(CLK_PERI_PWM1_PD, CLK_PAD_CLK25M, 2),
+ GATE_PERI0_EXT(CLK_PERI_PWM2_PD, CLK_PAD_CLK25M, 3),
+ GATE_PERI0_EXT(CLK_PERI_PWM3_PD, CLK_PAD_CLK25M, 4),
+ GATE_PERI0_EXT(CLK_PERI_PWM4_PD, CLK_PAD_CLK25M, 5),
+ GATE_PERI0_EXT(CLK_PERI_PWM5_PD, CLK_PAD_CLK25M, 6),
+ GATE_PERI0_EXT(CLK_PERI_PWM6_PD, CLK_PAD_CLK25M, 7),
+ GATE_PERI0_EXT(CLK_PERI_PWM7_PD, CLK_PAD_CLK25M, 8),
+ GATE_PERI0_EXT(CLK_PERI_PWM_PD, CLK_PAD_CLK25M, 9),
GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12),
GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13),
GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14),
@@ -495,7 +495,7 @@ static const struct mtk_gate peri_cgs[] = {
GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24),
GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25),
GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26),
- GATE_PERI0_XTAL(CLK_PERI_AUXADC_PD, CLK_XTAL, 27),
+ GATE_PERI0_EXT(CLK_PERI_AUXADC_PD, CLK_PAD_CLK25M, 27),
GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28),
GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29),
GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30),
@@ -616,7 +616,8 @@ static const struct mtk_clk_tree mt7622_apmixed_clk_tree = {
};
static const struct mtk_clk_tree mt7622_infra_clk_tree = {
- .xtal_rate = 25 * MHZ,
+ .ext_clk_rates = ext_clock_rates,
+ .num_ext_clks = ARRAY_SIZE(ext_clock_rates),
.muxes_offs = CLK_INFRA_MUX1_SEL,
.gates_offs = CLK_INFRA_DBGCLK_PD,
.muxes = infra_muxes,
@@ -626,7 +627,8 @@ static const struct mtk_clk_tree mt7622_infra_clk_tree = {
};
static const struct mtk_clk_tree mt7622_peri_clk_tree = {
- .xtal_rate = 25 * MHZ,
+ .ext_clk_rates = ext_clock_rates,
+ .num_ext_clks = ARRAY_SIZE(ext_clock_rates),
.muxes_offs = CLK_PERIBUS_SEL,
.gates_offs = CLK_PERI_THERM_PD,
.muxes = peri_muxes,
@@ -636,7 +638,8 @@ static const struct mtk_clk_tree mt7622_peri_clk_tree = {
};
static const struct mtk_clk_tree mt7622_clk_tree = {
- .xtal_rate = 25 * MHZ,
+ .ext_clk_rates = ext_clock_rates,
+ .num_ext_clks = ARRAY_SIZE(ext_clock_rates),
.fdivs_offs = CLK_TOP_TO_USB3_SYS,
.muxes_offs = CLK_TOP_AXI_SEL,
.fclks = top_fixed_clks,
--
2.43.0
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