[PATCH] arm: socfpga: Add fitImage for SPL programs periph RBF only

[dinesh.maniyam at altera.com]

From: Dinesh Maniyam <dinesh.maniyam at altera.com>

This is fitImage for programming peripheral RBF only in SPL, so that user
has option to program core RBF in U-Boot proper. The advantage of
programming core RBF in U-Boot proper especially for SDMMC boot the
performance can be increased up to around 90%, because program core RBF
in SPL hitting penalty on alignment issue in common FAT driver.

Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam at altera.com>
---
 .../fit_spl_fpga_periph_only.its              | 38 +++++++++++++++++++
 configs/socfpga_arria10_defconfig             |  2 +-
 include/configs/socfpga_common.h              |  2 +
 3 files changed, 41 insertions(+), 1 deletion(-)
 create mode 100644 board/altera/arria10-socdk/fit_spl_fpga_periph_only.its

diff --git a/board/altera/arria10-socdk/fit_spl_fpga_periph_only.its b/board/altera/arria10-socdk/fit_spl_fpga_periph_only.its
new file mode 100644
index 00000000000..06ba0328477
--- /dev/null
+++ b/board/altera/arria10-socdk/fit_spl_fpga_periph_only.its
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+ /*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+/dts-v1/;
+
+/ {
+	description = "FIT image with FPGA bistream";
+	#address-cells = <1>;
+
+	images {
+		fpga-periph-1 {
+			description = "FPGA peripheral bitstream";
+			data = /incbin/("../../../ghrd_10as066n2.periph.rbf");
+			type = "fpga";
+			arch = "arm";
+			compression = "none";
+		};
+
+		fpga-core-1 {
+			description = "FPGA core bitstream";
+			data = /incbin/("../../../ghrd_10as066n2.core.rbf");
+			type = "fpga";
+			arch = "arm";
+			compression = "none";
+		};
+	};
+
+	configurations {
+		default = "config-1";
+		config-1 {
+			description = "Boot with FPGA early IO release config";
+			fpga = "fpga-periph-1";
+		};
+	};
+};
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index b32f40ae408..1648e4bda4b 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -20,7 +20,7 @@ CONFIG_SPL_FIT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run fatscript;run prog_core;bridge enable;run distro_bootcmd"
 CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 2acfdc7df4a..2c01bf9d9fa 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -154,6 +154,8 @@
 	"pxefile_addr_r=0x02200000\0" \
 	"ramdisk_addr_r=0x02300000\0" \
 	"socfpga_legacy_reset_compat=1\0" \
+	"prog_core=if load mmc 0:1 ${loadaddr} fit_spl_fpga.itb;" \
+		"then fpga loadmk 0 ${loadaddr}:fpga-core-1; fi\0" \
 	BOOTENV
 
 #endif
-- 
2.43.7