[RFC PATCH 14/19] arm: mach-k3: j784s4: Enable DDR_RET exit for j742s2

[Prasanth Babu Mantena]

From: Abhash Kumar Jha <a-kumar2 at ti.com>

On the resume path, we perform an exit from the DDR self refresh state.
The self-refresh exit sequence is performed in a loop for each DDR controller.

The J784S4 has 4 ddr controllers and J742S2 has 2 controllers.

Select the number of ddr controllers on the basis of
CONFIG_TARGET_J742S2_R5_EVM build flag.

Signed-off-by: Abhash Kumar Jha <a-kumar2 at ti.com>
Signed-off-by: Prasanth Babu Mantena <p-mantena at ti.com>
---
 arch/arm/mach-k3/j784s4/j784s4_init.c | 18 +++++++++++-------
 board/ti/j784s4/evm.c                 |  2 +-
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c
index f039eb3f752..be04f88d23e 100644
--- a/arch/arm/mach-k3/j784s4/j784s4_init.c
+++ b/arch/arm/mach-k3/j784s4/j784s4_init.c
@@ -24,7 +24,11 @@
 #include "../sysfw-loader.h"
 #include "../common.h"
 
-#define J784S4_MAX_DDR_CONTROLLERS	4
+#if IS_ENABLED(CONFIG_TARGET_J742S2_R5_EVM)
+#define MAX_DDR_CONTROLLERS	2
+#else
+#define MAX_DDR_CONTROLLERS	4
+#endif
 
 #define CTRL_MMR_CFG0_AUDIO_REFCLK1_CTRL	0x001082e4
 #define AUDIO_REFCLK1_DEFAULT			0x1c
@@ -296,8 +300,8 @@ void k3_mem_init(void)
 	int ret, ctrl = 0;
 
 	if (IS_ENABLED(CONFIG_K3_J721E_DDRSS)) {
-		struct udevice *devs[J784S4_MAX_DDR_CONTROLLERS];
-		struct k3_ddrss_regs regs[J784S4_MAX_DDR_CONTROLLERS];
+		struct udevice *devs[MAX_DDR_CONTROLLERS];
+		struct k3_ddrss_regs regs[MAX_DDR_CONTROLLERS];
 
 		ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 		if (ret)
@@ -306,7 +310,7 @@ void k3_mem_init(void)
 		devs[0] = dev;
 		ctrl++;
 
-		while (ctrl < J784S4_MAX_DDR_CONTROLLERS) {
+		while (ctrl < MAX_DDR_CONTROLLERS) {
 			ret = uclass_next_device_err(&dev);
 			if (ret == -ENODEV)
 				break;
@@ -319,7 +323,7 @@ void k3_mem_init(void)
 
 		if (board_is_resuming()) {
 			/* exit DDRs from retention */
-			for (ctrl = 0; ctrl < J784S4_MAX_DDR_CONTROLLERS; ctrl++) {
+			for (ctrl = 0; ctrl < MAX_DDR_CONTROLLERS; ctrl++) {
 				k3_ddrss_lpddr4_exit_retention(devs[ctrl],
 							       &regs[ctrl]);
 			}
@@ -328,11 +332,11 @@ void k3_mem_init(void)
 			k3_deassert_DDR_RET();
 
 			/* restore DDR max frequency */
-			for (ctrl = 0; ctrl < J784S4_MAX_DDR_CONTROLLERS; ctrl++)
+			for (ctrl = 0; ctrl < MAX_DDR_CONTROLLERS; ctrl++)
 				k3_ddrss_lpddr4_change_freq(devs[ctrl]);
 
 			/* exit DDR from low power */
-			for (ctrl = 0; ctrl < J784S4_MAX_DDR_CONTROLLERS; ctrl++) {
+			for (ctrl = 0; ctrl < MAX_DDR_CONTROLLERS; ctrl++) {
 				k3_ddrss_lpddr4_exit_low_power(devs[ctrl],
 							       &regs[ctrl]);
 			}
diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c
index 3fd1a00c683..e7c427c71f0 100644
--- a/board/ti/j784s4/evm.c
+++ b/board/ti/j784s4/evm.c
@@ -64,7 +64,7 @@ int board_late_init(void)
 }
 #endif
 
-#if (IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_TARGET_J784S4_R5_EVM))
+#if (IS_ENABLED(CONFIG_SPL_BUILD) && (IS_ENABLED(CONFIG_TARGET_J784S4_R5_EVM) || IS_ENABLED(CONFIG_TARGET_J742S2_R5_EVM)))
 
 #define SCRATCH_PAD_REG_3 0xCB
 #define MAGIC_SUSPEND 0xBA
-- 
2.34.1