[PATCH 2/6] riscv: Extend noncached memory support to RISC-V

[Leo Yu-Chi Liang]

Extend the SYS_HAS_NONCACHED_MEMORY Kconfig to support RISC-V
in addition to ARM and MIPS, and add FTMAC100 to the list of
drivers that benefit from noncached memory.

The ftmac100 DMA descriptors needs to be marked uncacheable
to stay coherent for SW and HW on noncoherent platforms.

Also add MMU_SECTION_SIZE definition (1MB) to the RISC-V system
header, matching the MIPS convention used by the noncached memory
infrastructure.

Signed-off-by: Leo Yu-Chi Liang <ycliang at andestech.com>
---
 arch/Kconfig                    | 2 +-
 arch/riscv/include/asm/system.h | 6 ++++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/Kconfig b/arch/Kconfig
index fb3e8d598e7..b05f249b661 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -529,7 +529,7 @@ endmenu
 
 config SYS_HAS_NONCACHED_MEMORY
 	bool "Enable reserving a non-cached memory area for drivers"
-	depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
+	depends on (ARM || MIPS || RISCV) && (RTL8169 || MEDIATEK_ETH || FTMAC100)
 	help
 	  This is useful for drivers that would otherwise require a lot of
 	  explicit cache maintenance. For some drivers it's also impossible to
diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h
index 87a804bfd5f..b71bbeef1e2 100644
--- a/arch/riscv/include/asm/system.h
+++ b/arch/riscv/include/asm/system.h
@@ -25,6 +25,12 @@ struct event;
         csr_set(CSR_SSTATUS, __flags & SR_SIE); \
     } while (0)
 
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+/* 1MB granularity */
+#define MMU_SECTION_SHIFT	20
+#define MMU_SECTION_SIZE	BIT(MMU_SECTION_SHIFT)
+#endif /* CONFIG_SYS_NONCACHED_MEMORY */
+
 /* Hook to set up the CPU (called from SPL too) */
 int riscv_cpu_setup(void);
 
-- 
2.34.1