[PATCH] watchdog: designware: Fix probe when clk_enable return ENOSYS

[Jonas Karlman]

Rockchip SoCs typically reset with all (or most) clocks ungated. Because
of this, U-Boot clock drivers for Rockchip typically do not implement
the optional clk-uclass enable/disable ops.

Normal driver model behavior is to return -ENOSYS when an uclass ops
is not implemented.

Ignore -ENOSYS to allow the designware watchdog driver to be probed on
platforms that do not implement the clk-uclass enable/disable ops, e.g.
Rockchip RK3308.

Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
---
 drivers/watchdog/designware_wdt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c
index bd9d7105366..91228de5e8e 100644
--- a/drivers/watchdog/designware_wdt.c
+++ b/drivers/watchdog/designware_wdt.c
@@ -122,7 +122,7 @@ static int designware_wdt_probe(struct udevice *dev)
 		return ret;
 
 	ret = clk_enable(&clk);
-	if (ret)
+	if (ret && ret != -ENOSYS)
 		return ret;
 
 	priv->clk_khz = clk_get_rate(&clk) / 1000;
-- 
2.53.0