[PATCH V1 1/1] mtd/spi: add new part numbers

[Michal Simek]

út 28. 10. 2025 v 1:05 odesílatel Victor <vlim at gigadevice.com> napsal:
>
> GD25B512: ID C8401A, 3V 512Mbit
> https://download.gigadevice.com/Datasheet/DS-00649-GD25B512ME-Rev1.6.pdf
>
> GD55B01G: ID C8401B, 3V 1Gbit
> https://download.gigadevice.com/Datasheet/DS-00979-GD55B01GF-Rev1.1.pdf
>
> GD55B02G: ID C8401C, 3V 2Gbit
> https://download.gigadevice.com/Datasheet/DS-00980-GD55B02GF-Rev1.2.pdf
>
> GD55F01G: ID C8431B, 3V 1Gbit high performance
> I can send the datasheet via email
>
> GD55F02G: ID C8431C, 3V 2Gbit high performance
> I can send the datasheet via email.
>
> These parts are tested on Digilent Atry Z7 board and Xilinx Vitis.
>
> Signed-off-by: Victor <vlim at gigadevice.com>

Same comment as before. Full name and fix subject.

M

> ---
>  drivers/mtd/spi/spi-nor-ids.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index 666203c8485..5c6fc8a5155 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -123,6 +123,10 @@ const struct flash_info spi_nor_ids[] = {
>         SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)  },
>         {INFO("gd25b512", 0xc8401A, 0, 64 * 1024, 1024, SECT_4K |       SPI_NOR_HAS_TB |
>         SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
> +       {INFO("gd55b01g", 0xc8401B, 0, 64 * 1024, 2048, SECT_4K |       SPI_NOR_HAS_TB |
> +       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
> +       {INFO("gd55b02g", 0xc8401C, 0, 64 * 1024, 4096, SECT_4K |       SPI_NOR_HAS_TB |
> +       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
>         {INFO("gd25b512", 0xc8471A, 0, 64 * 1024, 1024, SECT_4K |
>         SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
>         {INFO("gd55b01g", 0xc8471B, 0, 64 * 1024, 2048, SECT_4K |
> @@ -137,6 +141,10 @@ const struct flash_info spi_nor_ids[] = {
>         SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
>         {INFO("gd55f512", 0xc8431A, 0, 64 * 1024, 1024, SECT_4K |
>         SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
> +       {INFO("gd55f01g", 0xc8431B, 0, 64 * 1024, 2048, SECT_4K |
> +       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
> +       {INFO("gd55f02g", 0xc8431C, 0, 64 * 1024, 4096, SECT_4K |
> +       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
>         {INFO("gd25t512", 0xc8461A, 0, 64 * 1024, 1024, SECT_4K |
>         SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
>         {INFO("gd55t01g", 0xc8461B, 0, 64 * 1024, 2048, SECT_4K |
> --
> 2.34.1
>


-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs