[PATCH 14/14] arch: arm: add Microchip LAN969x support
Robert Marko
robert.marko at sartura.hr
Thu Mar 26 12:26:55 CET 2026
Microchip LAN9696x is a Cortex-A53 based switch SoC.
Since Microchip also has LAN966x and SparX-5 families of switch SoC-s
lets add a generic architecture so those could be added in future as
well under the same architecture.
Support is included for the SoC and the EV23X71A board.
Signed-off-by: Robert Marko <robert.marko at sartura.hr>
---
arch/arm/Kconfig | 10 +
arch/arm/Makefile | 1 +
arch/arm/dts/Makefile | 2 +
arch/arm/dts/clk-lan9691.h | 24 +
arch/arm/dts/lan9691.dtsi | 545 +++++++++++++
arch/arm/dts/lan9696-ev23x71a-u-boot.dtsi | 18 +
arch/arm/dts/lan9696-ev23x71a.dts | 795 +++++++++++++++++++
arch/arm/dts/lan969x-u-boot.dtsi | 72 ++
arch/arm/mach-microchipsw/Kconfig | 31 +
arch/arm/mach-microchipsw/Makefile | 3 +
arch/arm/mach-microchipsw/include/mach/soc.h | 29 +
arch/arm/mach-microchipsw/lan969x/Makefile | 3 +
arch/arm/mach-microchipsw/lan969x/soc.c | 136 ++++
board/microchip/lan969x/Makefile | 3 +
board/microchip/lan969x/lan969x.c | 115 +++
configs/microchip_ev23x71a_defconfig | 77 ++
include/configs/lan969x.h | 36 +
17 files changed, 1900 insertions(+)
create mode 100644 arch/arm/dts/clk-lan9691.h
create mode 100644 arch/arm/dts/lan9691.dtsi
create mode 100644 arch/arm/dts/lan9696-ev23x71a-u-boot.dtsi
create mode 100644 arch/arm/dts/lan9696-ev23x71a.dts
create mode 100644 arch/arm/dts/lan969x-u-boot.dtsi
create mode 100644 arch/arm/mach-microchipsw/Kconfig
create mode 100644 arch/arm/mach-microchipsw/Makefile
create mode 100644 arch/arm/mach-microchipsw/include/mach/soc.h
create mode 100644 arch/arm/mach-microchipsw/lan969x/Makefile
create mode 100644 arch/arm/mach-microchipsw/lan969x/soc.c
create mode 100644 board/microchip/lan969x/Makefile
create mode 100644 board/microchip/lan969x/lan969x.c
create mode 100644 configs/microchip_ev23x71a_defconfig
create mode 100644 include/configs/lan969x.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cd6a454fd60..ebd9d96452f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -869,6 +869,14 @@ config ARCH_MEDIATEK
Support for the MediaTek SoCs family developed by MediaTek Inc.
Please refer to doc/README.mediatek for more information.
+config ARCH_MICROCHIPSW
+ bool "Microchip switch SoCs"
+ select DM
+ select OF_CONTROL
+ imply CMD_DM
+ help
+ Support for Microchip switch focused SoC-s.
+
config ARCH_MMP
bool "Marvell MMP"
select ARM64
@@ -2400,6 +2408,8 @@ source "arch/arm/mach-nexell/Kconfig"
source "arch/arm/mach-npcm/Kconfig"
+source "arch/arm/mach-microchipsw/Kconfig"
+
source "board/armltd/total_compute/Kconfig"
source "board/armltd/corstone1000/Kconfig"
source "board/bosch/shc/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index b36b0742580..2d5e4836b06 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -70,6 +70,7 @@ machine-$(CONFIG_ARCH_KIRKWOOD) += kirkwood
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
machine-$(CONFIG_ARCH_MESON) += meson
+machine-$(CONFIG_ARCH_MICROCHIPSW) += microchipsw
machine-$(CONFIG_ARCH_MMP) += mmp
machine-$(CONFIG_ARCH_MVEBU) += mvebu
machine-$(CONFIG_ARCH_NEXELL) += nexell
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 82ad3035308..ec6ba8c5f55 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1210,6 +1210,8 @@ dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \
dtb-$(CONFIG_TARGET_COREPRIMEVELTE) += pxa1908-samsung-coreprimevelte.dtb
+dtb-$(CONFIG_ARCH_MICROCHIPSW) += lan9696-ev23x71a.dtb
+
include $(srctree)/scripts/Makefile.dts
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/clk-lan9691.h b/arch/arm/dts/clk-lan9691.h
new file mode 100644
index 00000000000..0f2d7a0f881
--- /dev/null
+++ b/arch/arm/dts/clk-lan9691.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */
+
+#ifndef _DTS_CLK_LAN9691_H
+#define _DTS_CLK_LAN9691_H
+
+#define GCK_ID_QSPI0 0
+#define GCK_ID_QSPI2 1
+#define GCK_ID_SDMMC0 2
+#define GCK_ID_SDMMC1 3
+#define GCK_ID_MCAN0 4
+#define GCK_ID_MCAN1 5
+#define GCK_ID_FLEXCOM0 6
+#define GCK_ID_FLEXCOM1 7
+#define GCK_ID_FLEXCOM2 8
+#define GCK_ID_FLEXCOM3 9
+#define GCK_ID_TIMER 10
+#define GCK_ID_USB_REFCLK 11
+
+/* Gate clocks */
+#define GCK_GATE_USB_DRD 12
+#define GCK_GATE_MCRAMC 13
+#define GCK_GATE_HMATRIX 14
+
+#endif
diff --git a/arch/arm/dts/lan9691.dtsi b/arch/arm/dts/lan9691.dtsi
new file mode 100644
index 00000000000..b79923fba00
--- /dev/null
+++ b/arch/arm/dts/lan9691.dtsi
@@ -0,0 +1,545 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ */
+
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mfd/at91-usart.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+
+#include "clk-lan9691.h"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ model = "Microchip LAN969x";
+ compatible = "microchip,lan9691";
+ interrupt-parent = <&gic>;
+
+ clocks {
+ fx100_clk: fx100-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <320000000>;
+ };
+
+ cpu_clk: cpu-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000000>;
+ };
+
+ ddr_clk: ddr-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <600000000>;
+ };
+
+ fabric_clk: fabric-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ next-level-cache = <&l2_0>;
+ };
+
+ l2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Secure Phys IRQ */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Non-secure Phys IRQ */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virt IRQ */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hyp IRQ */
+ };
+
+ axi: axi {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usb: usb at 300000 {
+ compatible = "microchip,lan9691-dwc3", "snps,dwc3";
+ reg = <0x300000 0x80000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks GCK_GATE_USB_DRD>,
+ <&clks GCK_ID_USB_REFCLK>;
+ clock-names = "bus_early", "ref";
+ assigned-clocks = <&clks GCK_ID_USB_REFCLK>;
+ assigned-clock-rates = <60000000>;
+ maximum-speed = "high-speed";
+ dr_mode = "host";
+ status = "disabled";
+ };
+
+ otp: otp at e0021000 {
+ compatible = "microchip,lan9691-otpc";
+ reg = <0xe0021000 0x1000>;
+ };
+
+ flx0: flexcom at e0040000 {
+ compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
+ reg = <0xe0040000 0x100>;
+ ranges = <0x0 0xe0040000 0x800>;
+ clocks = <&clks GCK_ID_FLEXCOM0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usart0: serial at 200 {
+ compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
+ <&dma AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+ status = "disabled";
+ };
+
+ spi0: spi at 400 {
+ compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
+ <&dma AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ clock-names = "spi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ i2c0: i2c at 600 {
+ compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
+ <&dma AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ flx1: flexcom at e0044000 {
+ compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
+ reg = <0xe0044000 0x100>;
+ ranges = <0x0 0xe0044000 0x800>;
+ clocks = <&clks GCK_ID_FLEXCOM1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usart1: serial at 200 {
+ compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
+ <&dma AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+ status = "disabled";
+ };
+
+ spi1: spi at 400 {
+ compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
+ <&dma AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ clock-names = "spi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at 600 {
+ compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
+ <&dma AT91_XDMAC_DT_PERID(2)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ trng: rng at e0048000 {
+ compatible = "microchip,lan9691-trng", "atmel,at91sam9g45-trng";
+ reg = <0xe0048000 0x100>;
+ clocks = <&fabric_clk>;
+ status = "disabled";
+ };
+
+ aes: crypto at e004c000 {
+ compatible = "microchip,lan9691-aes", "atmel,at91sam9g46-aes";
+ reg = <0xe004c000 0x100>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(12)>,
+ <&dma AT91_XDMAC_DT_PERID(13)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ clock-names = "aes_clk";
+ status = "disabled";
+ };
+
+ flx2: flexcom at e0060000 {
+ compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
+ reg = <0xe0060000 0x100>;
+ ranges = <0x0 0xe0060000 0x800>;
+ clocks = <&clks GCK_ID_FLEXCOM2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usart2: serial at 200 {
+ compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(7)>,
+ <&dma AT91_XDMAC_DT_PERID(6)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+ status = "disabled";
+ };
+
+ spi2: spi at 400 {
+ compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(7)>,
+ <&dma AT91_XDMAC_DT_PERID(6)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ clock-names = "spi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at 600 {
+ compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(7)>,
+ <&dma AT91_XDMAC_DT_PERID(6)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ flx3: flexcom at e0064000 {
+ compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
+ reg = <0xe0064000 0x100>;
+ ranges = <0x0 0xe0064000 0x800>;
+ clocks = <&clks GCK_ID_FLEXCOM3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usart3: serial at 200 {
+ compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(9)>,
+ <&dma AT91_XDMAC_DT_PERID(8)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ clock-names = "usart";
+ atmel,fifo-size = <32>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+ status = "disabled";
+ };
+
+ spi3: spi at 400 {
+ compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(9)>,
+ <&dma AT91_XDMAC_DT_PERID(8)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ clock-names = "spi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ i2c3: i2c at 600 {
+ compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(9)>,
+ <&dma AT91_XDMAC_DT_PERID(8)>;
+ dma-names = "tx", "rx";
+ clocks = <&fabric_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ dma: dma-controller at e0068000 {
+ compatible = "microchip,lan9691-dma", "microchip,sama7g5-dma";
+ reg = <0xe0068000 0x1000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <16>;
+ #dma-cells = <1>;
+ clocks = <&fabric_clk>;
+ clock-names = "dma_clk";
+ };
+
+ sha: crypto at e006c000 {
+ compatible = "microchip,lan9691-sha", "atmel,at91sam9g46-sha";
+ reg = <0xe006c000 0xec>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma AT91_XDMAC_DT_PERID(14)>;
+ dma-names = "tx";
+ clocks = <&fabric_clk>;
+ clock-names = "sha_clk";
+ status = "disabled";
+ };
+
+ timer: timer at e008c000 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0xe008c000 0x400>;
+ clocks = <&fabric_clk>;
+ clock-names = "timer";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ watchdog: watchdog at e0090000 {
+ compatible = "snps,dw-wdt";
+ reg = <0xe0090000 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&fabric_clk>;
+ };
+
+ cpu_ctrl: syscon at e00c0000 {
+ compatible = "microchip,lan966x-cpu-syscon", "syscon";
+ reg = <0xe00c0000 0x350>;
+ };
+
+ switch: switch at e00c0000 {
+ compatible = "microchip,lan9691-switch";
+ reg = <0xe00c0000 0x0010000>,
+ <0xe2010000 0x1410000>;
+ reg-names = "cpu", "devices";
+ interrupt-names = "xtr", "fdma", "ptp";
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&reset 0>;
+ reset-names = "switch";
+ status = "disabled";
+ };
+
+ clks: clock-controller at e00c00b4 {
+ compatible = "microchip,lan9691-gck";
+ reg = <0xe00c00b4 0x30>, <0xe00c0308 0x4>;
+ #clock-cells = <1>;
+ clocks = <&cpu_clk>, <&ddr_clk>, <&fx100_clk>;
+ clock-names = "cpu", "ddr", "sys";
+ };
+
+ qspi0: spi at e0804000 {
+ compatible = "microchip,lan9691-qspi";
+ reg = <0xe0804000 0x00000100>,
+ <0x20000000 0x08000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&fabric_clk>, <&clks GCK_ID_QSPI0>;
+ clock-names = "pclk", "gclk";
+ assigned-clocks = <&clks GCK_ID_QSPI0>;
+ assigned-clock-rates = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ sdmmc0: mmc at e0830000 {
+ compatible = "microchip,lan9691-sdhci";
+ reg = <0xe0830000 0x00000300>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks GCK_ID_SDMMC0>, <&clks GCK_ID_SDMMC0>;
+ clock-names = "hclock", "multclk";
+ assigned-clocks = <&clks GCK_ID_SDMMC0>;
+ assigned-clock-rates = <100000000>;
+ status = "disabled";
+ };
+
+ sdmmc1: mmc at e0838000 {
+ compatible = "microchip,lan9691-sdhci";
+ reg = <0xe0838000 0x00000300>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks GCK_ID_SDMMC1>, <&clks GCK_ID_SDMMC1>;
+ clock-names = "hclock", "multclk";
+ assigned-clocks = <&clks GCK_ID_SDMMC1>;
+ assigned-clock-rates = <45000000>;
+ status = "disabled";
+ };
+
+ qspi2: spi at e0834000 {
+ compatible = "microchip,lan9691-qspi";
+ reg = <0xe0834000 0x00000100>,
+ <0x30000000 0x04000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&fabric_clk>, <&clks GCK_ID_QSPI2>;
+ clock-names = "pclk", "gclk";
+ assigned-clocks = <&clks GCK_ID_QSPI2>;
+ assigned-clock-rates = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ reset: reset-controller at e201000c {
+ compatible = "microchip,lan9691-switch-reset",
+ "microchip,lan966x-switch-reset";
+ reg = <0xe201000c 0x4>;
+ reg-names = "gcb";
+ #reset-cells = <1>;
+ cpu-syscon = <&cpu_ctrl>;
+ };
+
+ gpio: pinctrl at e20100d4 {
+ compatible = "microchip,lan9691-pinctrl";
+ reg = <0xe20100d4 0xd4>,
+ <0xe2010370 0xa8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 66>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ };
+
+ mdio0: mdio at e20101a8 {
+ compatible = "microchip,lan9691-miim", "mscc,ocelot-miim";
+ reg = <0xe20101a8 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&fx100_clk>;
+ status = "disabled";
+ };
+
+ mdio1: mdio at e20101cc {
+ compatible = "microchip,lan9691-miim", "mscc,ocelot-miim";
+ reg = <0xe20101cc 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&fx100_clk>;
+ status = "disabled";
+ };
+
+ sgpio: gpio at e2010230 {
+ compatible = "microchip,lan9691-sgpio", "microchip,sparx5-sgpio";
+ reg = <0xe2010230 0x118>;
+ clocks = <&fx100_clk>;
+ resets = <&reset 0>;
+ reset-names = "switch";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sgpio_in: gpio at 0 {
+ compatible = "microchip,lan9691-sgpio-bank",
+ "microchip,sparx5-sgpio-bank";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ sgpio_out: gpio at 1 {
+ compatible = "microchip,lan9691-sgpio-bank",
+ "microchip,sparx5-sgpio-bank";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ };
+ };
+
+ tmon: hwmon at e2020100 {
+ compatible = "microchip,lan9691-temp", "microchip,sparx5-temp";
+ reg = <0xe2020100 0xc>;
+ clocks = <&fx100_clk>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ serdes: serdes at e3410000 {
+ compatible = "microchip,lan9691-serdes";
+ reg = <0xe3410000 0x150000>;
+ #phy-cells = <1>;
+ clocks = <&fabric_clk>;
+ };
+
+ gic: interrupt-controller at e8c11000 {
+ compatible = "arm,gic-400";
+ reg = <0xe8c11000 0x1000>, /* Distributor GICD_ */
+ <0xe8c12000 0x2000>, /* CPU interface GICC_ */
+ <0xe8c14000 0x2000>, /* Virt interface control */
+ <0xe8c16000 0x2000>; /* Virt CPU interface */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+};
diff --git a/arch/arm/dts/lan9696-ev23x71a-u-boot.dtsi b/arch/arm/dts/lan9696-ev23x71a-u-boot.dtsi
new file mode 100644
index 00000000000..bbbb578cc57
--- /dev/null
+++ b/arch/arm/dts/lan9696-ev23x71a-u-boot.dtsi
@@ -0,0 +1,18 @@
+
+#include <dt-bindings/mscc/sparx5_data.h>
+
+&switch {
+ /delete-node/ ethernet-ports;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port29: port at 29 {
+ reg = <29>;
+ phy-handle = <&phy3>;
+ phy-mode = "rgmii-rxid";
+ phys = <IF_RGMII>;
+ };
+ };
+};
diff --git a/arch/arm/dts/lan9696-ev23x71a.dts b/arch/arm/dts/lan9696-ev23x71a.dts
new file mode 100644
index 00000000000..4935b6d7b14
--- /dev/null
+++ b/arch/arm/dts/lan9696-ev23x71a.dts
@@ -0,0 +1,795 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include "lan9691.dtsi"
+
+/ {
+ model = "Microchip EV23X71A";
+ compatible = "microchip,ev23x71a", "microchip,lan9696", "microchip,lan9691";
+
+ aliases {
+ serial0 = &usart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 60 GPIO_ACTIVE_LOW>;
+ open-source;
+ priority = <200>;
+ };
+
+ i2c-mux {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c3>;
+ idle-state = <0x8>;
+ mux-gpios = <&sgpio_out 0 1 GPIO_ACTIVE_HIGH>,
+ <&sgpio_out 0 2 GPIO_ACTIVE_HIGH>,
+ <&sgpio_out 0 3 GPIO_ACTIVE_HIGH>;
+ settle-time-us = <100>;
+
+ i2c_sfp0: i2c at 0 {
+ reg = <0x0>;
+ };
+
+ i2c_sfp1: i2c at 1 {
+ reg = <0x1>;
+ };
+
+ i2c_sfp2: i2c at 2 {
+ reg = <0x2>;
+ };
+
+ i2c_sfp3: i2c at 3 {
+ reg = <0x3>;
+ };
+
+ i2c_poe: i2c at 7 {
+ reg = <0x7>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-status {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio 61 GPIO_ACTIVE_LOW>;
+ };
+
+ led-sfp1-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <0>;
+ gpios = <&sgpio_out 6 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-sfp1-yellow {
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <0>;
+ gpios = <&sgpio_out 6 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-sfp2-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <1>;
+ gpios = <&sgpio_out 7 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-sfp2-yellow {
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <1>;
+ gpios = <&sgpio_out 7 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-sfp3-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <2>;
+ gpios = <&sgpio_out 8 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-sfp3-yellow {
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <2>;
+ gpios = <&sgpio_out 8 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-sfp4-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <3>;
+ gpios = <&sgpio_out 9 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led-sfp4-yellow {
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <3>;
+ gpios = <&sgpio_out 9 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+ mux-gpios = <&sgpio_out 1 2 GPIO_ACTIVE_LOW>,
+ <&sgpio_out 1 3 GPIO_ACTIVE_LOW>;
+ };
+
+ sfp0: sfp0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp0>;
+ tx-disable-gpios = <&sgpio_out 6 2 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in 6 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in 6 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in 6 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp1: sfp1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp1>;
+ tx-disable-gpios = <&sgpio_out 7 2 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in 7 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in 7 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in 7 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp2: sfp2 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp2>;
+ tx-disable-gpios = <&sgpio_out 8 2 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in 8 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in 8 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in 8 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp3: sfp3 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp3>;
+ tx-disable-gpios = <&sgpio_out 9 2 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in 9 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in 9 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in 9 2 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&gpio {
+ emmc_sd_pins: emmc-sd-pins {
+ /* eMMC_SD - CMD, CLK, D0, D1, D2, D3, D4, D5, D6, D7, RSTN */
+ pins = "GPIO_14", "GPIO_15", "GPIO_16", "GPIO_17",
+ "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_21",
+ "GPIO_22", "GPIO_23", "GPIO_24";
+ function = "emmc_sd";
+ };
+
+ fan_pins: fan-pins {
+ pins = "GPIO_25", "GPIO_26";
+ function = "fan";
+ };
+
+ fc0_pins: fc0-pins {
+ pins = "GPIO_3", "GPIO_4";
+ function = "fc";
+ };
+
+ fc2_pins: fc2-pins {
+ pins = "GPIO_64", "GPIO_65", "GPIO_66";
+ function = "fc";
+ };
+
+ fc3_pins: fc3-pins {
+ pins = "GPIO_55", "GPIO_56";
+ function = "fc";
+ };
+
+ mdio_irq_pins: mdio-irq-pins {
+ pins = "GPIO_11";
+ function = "miim_irq";
+ };
+
+ mdio_pins: mdio-pins {
+ pins = "GPIO_9", "GPIO_10";
+ function = "miim";
+ };
+
+ ptp_ext_pins: ptp-ext-pins {
+ pins = "GPIO_59";
+ function = "ptpsync_5";
+ };
+
+ ptp_out_pins: ptp-out-pins {
+ pins = "GPIO_58";
+ function = "ptpsync_4";
+ };
+
+ sgpio_pins: sgpio-pins {
+ /* SCK, D0, D1, LD */
+ pins = "GPIO_5", "GPIO_6", "GPIO_7", "GPIO_8";
+ function = "sgpio_a";
+ };
+
+ usb_over_pins: usb-over-pins {
+ pins = "GPIO_13";
+ function = "usb_over_detect";
+ };
+
+ usb_power_pins: usb-power-pins {
+ pins = "GPIO_1";
+ function = "usb_power";
+ };
+
+ usb_rst_pins: usb-rst-pins {
+ pins = "GPIO_12";
+ function = "usb2phy_rst";
+ };
+
+ usb_ulpi_pins: usb-ulpi-pins {
+ pins = "GPIO_30", "GPIO_31", "GPIO_32", "GPIO_33",
+ "GPIO_34", "GPIO_35", "GPIO_36", "GPIO_37",
+ "GPIO_38", "GPIO_39", "GPIO_40", "GPIO_41";
+ function = "usb_ulpi";
+ };
+};
+
+&flx0 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "okay";
+};
+
+&flx2 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
+ status = "okay";
+};
+
+&flx3 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-0 = <&fc3_pins>;
+ pinctrl-names = "default";
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
+ i2c-sda-hold-time-ns = <1500>;
+ status = "okay";
+};
+
+&mdio0 {
+ pinctrl-0 = <&mdio_pins>, <&mdio_irq_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio 62 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ phy3: phy at 3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy4: phy at 4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy5: phy at 5 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <5>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy6: phy at 6 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <6>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy7: phy at 7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy8: phy at 8 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <8>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy9: phy at 9 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <9>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy10: phy at 10 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <10>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy11: phy at 11 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <11>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy12: phy at 12 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <12>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy13: phy at 13 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <13>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy14: phy at 14 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <14>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy15: phy at 15 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <15>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy16: phy at 16 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <16>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy17: phy at 17 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <17>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy18: phy at 18 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <18>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy19: phy at 19 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <19>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy20: phy at 20 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <20>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy21: phy at 21 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <21>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy22: phy at 22 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <22>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy23: phy at 23 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <23>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy24: phy at 24 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <24>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy25: phy at 25 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <25>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy26: phy at 26 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <26>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+
+ phy27: phy at 27 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <27>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio>;
+ };
+};
+
+&otp {
+ nvmem-layout {
+ compatible = "microchip,otp-layout";
+
+ base_mac_address: base-mac-address {
+ #nvmem-cell-cells = <1>;
+ };
+ };
+};
+
+&qspi0 {
+ status = "okay";
+
+ flash at 0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ m25p,fast-read;
+ };
+};
+
+&sdmmc0 {
+ pinctrl-0 = <&emmc_sd_pins>;
+ pinctrl-names = "default";
+ max-frequency = <100000000>;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ disable-wp;
+ status = "okay";
+};
+
+&serdes {
+ status = "okay";
+};
+
+&sgpio {
+ pinctrl-0 = <&sgpio_pins>;
+ pinctrl-names = "default";
+ microchip,sgpio-port-ranges = <0 1>, <6 9>;
+ status = "okay";
+
+ gpio at 0 {
+ ngpios = <128>;
+ };
+ gpio at 1 {
+ ngpios = <128>;
+ };
+};
+
+&spi2 {
+ pinctrl-0 = <&fc2_pins>;
+ pinctrl-names = "default";
+ cs-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&switch {
+ pinctrl-0 = <&ptp_out_pins>, <&ptp_ext_pins>;
+ pinctrl-names = "default";
+ nvmem-cells = <&base_mac_address 0>;
+ nvmem-cell-names = "mac-address";
+ status = "okay";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port0: port at 0 {
+ reg = <0>;
+ phy-handle = <&phy4>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 0>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port1: port at 1 {
+ reg = <1>;
+ phy-handle = <&phy5>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 0>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port2: port at 2 {
+ reg = <2>;
+ phy-handle = <&phy6>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 0>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port3: port at 3 {
+ reg = <3>;
+ phy-handle = <&phy7>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 0>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port4: port at 4 {
+ reg = <4>;
+ phy-handle = <&phy8>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 1>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port5: port at 5 {
+ reg = <5>;
+ phy-handle = <&phy9>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 1>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port6: port at 6 {
+ reg = <6>;
+ phy-handle = <&phy10>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 1>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port7: port at 7 {
+ reg = <7>;
+ phy-handle = <&phy11>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 1>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port8: port at 8 {
+ reg = <8>;
+ phy-handle = <&phy12>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 2>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port9: port at 9 {
+ reg = <9>;
+ phy-handle = <&phy13>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 2>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port10: port at 10 {
+ reg = <10>;
+ phy-handle = <&phy14>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 2>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port11: port at 11 {
+ reg = <11>;
+ phy-handle = <&phy15>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 2>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port12: port at 12 {
+ reg = <12>;
+ phy-handle = <&phy16>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 3>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port13: port at 13 {
+ reg = <13>;
+ phy-handle = <&phy17>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 3>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port14: port at 14 {
+ reg = <14>;
+ phy-handle = <&phy18>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 3>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port15: port at 15 {
+ reg = <15>;
+ phy-handle = <&phy19>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 3>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port16: port at 16 {
+ reg = <16>;
+ phy-handle = <&phy20>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 4>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port17: port at 17 {
+ reg = <17>;
+ phy-handle = <&phy21>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 4>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port18: port at 18 {
+ reg = <18>;
+ phy-handle = <&phy22>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 4>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port19: port at 19 {
+ reg = <19>;
+ phy-handle = <&phy23>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 4>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port20: port at 20 {
+ reg = <20>;
+ phy-handle = <&phy24>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 5>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port21: port at 21 {
+ reg = <21>;
+ phy-handle = <&phy25>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 5>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port22: port at 22 {
+ reg = <22>;
+ phy-handle = <&phy26>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 5>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port23: port at 23 {
+ reg = <23>;
+ phy-handle = <&phy27>;
+ phy-mode = "qsgmii";
+ phys = <&serdes 5>;
+ microchip,bandwidth = <1000>;
+ };
+
+ port24: port at 24 {
+ reg = <24>;
+ phys = <&serdes 6>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp0>;
+ managed = "in-band-status";
+ microchip,bandwidth = <10000>;
+ microchip,sd-sgpio = <24>;
+ };
+
+ port25: port at 25 {
+ reg = <25>;
+ phys = <&serdes 7>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp1>;
+ managed = "in-band-status";
+ microchip,bandwidth = <10000>;
+ microchip,sd-sgpio = <28>;
+ };
+
+ port26: port at 26 {
+ reg = <26>;
+ phys = <&serdes 8>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp2>;
+ managed = "in-band-status";
+ microchip,bandwidth = <10000>;
+ microchip,sd-sgpio = <32>;
+ };
+
+ port27: port at 27 {
+ reg = <27>;
+ phys = <&serdes 9>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp3>;
+ managed = "in-band-status";
+ microchip,bandwidth = <10000>;
+ microchip,sd-sgpio = <36>;
+ };
+
+ port29: port at 29 {
+ reg = <29>;
+ phy-handle = <&phy3>;
+ phy-mode = "rgmii-id";
+ microchip,bandwidth = <1000>;
+ };
+ };
+};
+
+&tmon {
+ pinctrl-0 = <&fan_pins>;
+ pinctrl-names = "default";
+};
+
+&usart0 {
+ pinctrl-0 = <&fc0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usb {
+ pinctrl-0 = <&usb_ulpi_pins>, <&usb_rst_pins>, <&usb_over_pins>, <&usb_power_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/arch/arm/dts/lan969x-u-boot.dtsi b/arch/arm/dts/lan969x-u-boot.dtsi
new file mode 100644
index 00000000000..066e0697d77
--- /dev/null
+++ b/arch/arm/dts/lan969x-u-boot.dtsi
@@ -0,0 +1,72 @@
+
+&switch {
+ /delete-property/ reg;
+ /delete-property/ reg-names;
+
+ reg = <0xe2900000 0x100000>, // ANA_AC
+ <0xe2400000 0x100000>, // ANA_CL
+ <0xe2800000 0x100000>, // ANA_L2
+ <0xe2480000 0x100000>, // ANA_L3
+ <0xe3200000 0x10000>, // ASM
+ <0xe2060000 0x10000>, // LRN
+ <0xe20b0000 0x10000>, // QFWD
+ <0xe2030000 0x20000>, // DEVCPU_QS
+ <0xe20a0000 0x10000>, // QSYS
+ <0xe2600000 0x80000>, // REW
+ <0xe2a00000 0x80000>, // VOP
+ <0xe30ec000 0x80000>, // DSM
+ <0xe22c0000 0x80000>, // EACL
+ <0xe2080000 0x80000>, // VCAP_SUPER
+ <0xe2580000 0x80000>, // HSCH
+ <0xe30f0000 0x10000>, // PORT_CONF
+ <0xe20c0000 0x10000>, // XQS
+ <0xe3408000 0x10000>, // HSIO
+ <0xe2010000 0x10000>, // GCB
+ <0xe00c0000 0x10000>, // CPU
+ <0xe2040000 0x10000>, // PTP
+ <0xe3004000 0x4000>, // DEV2G5_0
+ <0xe3010000 0x4000>, // DEV2G5_1
+ <0xe3014000 0x4000>, // DEV2G5_2
+ <0xe3018000 0x4000>, // DEV2G5_3
+ <0xe301c000 0x4000>, // DEV2G5_4
+ <0xe3028000 0x4000>, // DEV2G5_5
+ <0xe302c000 0x4000>, // DEV2G5_6
+ <0xe3030000 0x4000>, // DEV2G5_7
+ <0xe3034000 0x4000>, // DEV2G5_8
+ <0xe3040000 0x4000>, // DEV2G5_9
+ <0xe304c000 0x4000>, // DEV2G5_10
+ <0xe3050000 0x4000>, // DEV2G5_11
+ <0xe3054000 0x4000>, // DEV2G5_12
+ <0xe3060000 0x4000>, // DEV2G5_13
+ <0xe306c000 0x4000>, // DEV2G5_14
+ <0xe3070000 0x4000>, // DEV2G5_15
+ <0xe3074000 0x4000>, // DEV2G5_16
+ <0xe3080000 0x4000>, // DEV2G5_17
+ <0xe308c000 0x4000>, // DEV2G5_18
+ <0xe3090000 0x4000>, // DEV2G5_19
+ <0xe3094000 0x4000>, // DEV2G5_20
+ <0xe30a0000 0x4000>, // DEV2G5_21
+ <0xe30ac000 0x4000>, // DEV2G5_22
+ <0xe30b0000 0x4000>, // DEV2G5_23
+ <0xe30b4000 0x4000>, // DEV2G5_24
+ <0xe30c0000 0x4000>, // DEV2G5_25
+ <0xe30cc000 0x4000>, // DEV2G5_26
+ <0xe30d8000 0x4000>, // DEV2G5_27
+ <0xe30e4000 0x4000>, // DEV2G5_28 (RGMII)
+ <0xe30e8000 0x4000>, // DEV2G5_29 (RGMII)
+ <0xe3410000 0x150000>; // SERDES
+ reg-names =
+ "ana_ac", "ana_cl", "ana_l2", "ana_l3",
+ "asm", "lrn", "qfwd", "qs",
+ "qsys", "rew", "vop", "dsm",
+ "eacl", "vcap_super", "hsch", "port_conf", "xqs",
+ "hsio", "gcb", "cpu", "ptp",
+ "port0", "port1", "port2", "port3",
+ "port4", "port5", "port6", "port7", "port8",
+ "port9", "port10", "port11", "port12", "port13",
+ "port14", "port15", "port16", "port17", "port18",
+ "port19", "port20", "port21", "port22", "port23",
+ "port24", "port25", "port26", "port27", "port28",
+ "port29";
+ clocks = <&fabric_clk>;
+};
diff --git a/arch/arm/mach-microchipsw/Kconfig b/arch/arm/mach-microchipsw/Kconfig
new file mode 100644
index 00000000000..aadd6beb00d
--- /dev/null
+++ b/arch/arm/mach-microchipsw/Kconfig
@@ -0,0 +1,31 @@
+if ARCH_MICROCHIPSW
+
+config SYS_SOC
+ default "microchipsw"
+
+config SYS_VENDOR
+ default "microchip"
+
+choice
+ prompt "Microchip switch SoC select"
+
+config TARGET_LAN969X
+ bool "Microchip LAN969x SoC"
+ select ARM64
+ select ARCH_SUPPORT_TFABOOT
+ select DM_SERIAL
+ select DM_GPIO
+ help
+ Support for Microchip LAN969X reference board platform.
+
+endchoice
+
+config SYS_BOARD
+ string "Board name"
+ default "lan969x" if TARGET_LAN969X
+ default ""
+
+config SYS_CONFIG_NAME
+ default "lan969x" if TARGET_LAN969X
+
+endif
diff --git a/arch/arm/mach-microchipsw/Makefile b/arch/arm/mach-microchipsw/Makefile
new file mode 100644
index 00000000000..39eca321705
--- /dev/null
+++ b/arch/arm/mach-microchipsw/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_TARGET_LAN969X) += lan969x/
diff --git a/arch/arm/mach-microchipsw/include/mach/soc.h b/arch/arm/mach-microchipsw/include/mach/soc.h
new file mode 100644
index 00000000000..cd1d61ff121
--- /dev/null
+++ b/arch/arm/mach-microchipsw/include/mach/soc.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _MICROCHIPSW_SOC_H_
+#define _MICROCHIPSW_SOC_H_
+
+#if defined(CONFIG_TARGET_LAN969X)
+#include <asm/types.h>
+
+typedef enum {
+ BOOT_SOURCE_EMMC = 0,
+ BOOT_SOURCE_QSPI,
+ BOOT_SOURCE_SDMMC,
+ BOOT_SOURCE_NONE
+} boot_source_type_t;
+
+phys_size_t tfa_get_dram_size(void);
+
+boot_source_type_t tfa_get_boot_source(void);
+
+int tfa_get_board_number(void);
+
+phys_size_t tfa_get_sram_info(int ix, phys_addr_t *start);
+
+#endif /* CONFIG_TARGET_LAN969X */
+#endif /* _LAN969X_SOC_H_ */
diff --git a/arch/arm/mach-microchipsw/lan969x/Makefile b/arch/arm/mach-microchipsw/lan969x/Makefile
new file mode 100644
index 00000000000..efa5153a3b7
--- /dev/null
+++ b/arch/arm/mach-microchipsw/lan969x/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y = soc.o
diff --git a/arch/arm/mach-microchipsw/lan969x/soc.c b/arch/arm/mach-microchipsw/lan969x/soc.c
new file mode 100644
index 00000000000..d094b52f888
--- /dev/null
+++ b/arch/arm/mach-microchipsw/lan969x/soc.c
@@ -0,0 +1,136 @@
+#include <asm/io.h>
+#include <dm/uclass.h>
+#include <linux/arm-smccc.h>
+#include <linux/bitfield.h>
+
+#include <asm/arch/soc.h>
+
+#define CPU_RESET_PROT_STAT 0xe00c0088
+#define SYS_RST_PROT_VCORE_M BIT(5)
+
+#define GCB_CHIP_ID 0xe2010000
+#define PART_ID_M GENMASK(27, 12)
+
+#define GCB_SOFT_RST 0xe201000c
+#define CHIP_SOFT_RST_M BIT(0)
+
+#define SIP_SVC_UID 0x8200ff01
+#define SIP_SVC_VERSION 0x8200ff02
+#define SIP_SVC_GET_BOOTSRC 0x8200ff09
+#define SIP_SVC_GET_DDR_SIZE 0x8200ff0a
+#define SIP_SVC_GET_BOARD_NO 0x8200ff0b
+#define SIP_SVC_SRAM_INFO 0x8200ff0d
+
+enum lan969x_part_id {
+ LAN9691VAO = 0x9691, /* lan969x-40-VAO */
+ LAN9692VAO = 0x9692, /* lan969x-65-VAO */
+ LAN9693VAO = 0x9693, /* lan969x-100-VAO */
+ LAN9694 = 0x9694, /* lan969x-40 */
+ LAN9694TSN = 0x9695, /* lan969x-40-TSN */
+ LAN9694RED = 0x969A, /* lan969x-40-RED */
+ LAN9696 = 0x9696, /* lan969x-60 */
+ LAN9696TSN = 0x9697, /* lan969x-60-TSN */
+ LAN9696RED = 0x969B, /* lan969x-60-RED */
+ LAN9698 = 0x9698, /* lan969x-100 */
+ LAN9698TSN = 0x9699, /* lan969x-100-TSN */
+ LAN9698RED = 0x969C, /* lan969x-100-RED */
+};
+
+boot_source_type_t tfa_get_boot_source(void)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(SIP_SVC_GET_BOOTSRC, -1, 0, 0, 0, 0, 0, 0, &res);
+ if (res.a0)
+ return BOOT_SOURCE_NONE;
+
+ return (boot_source_type_t) res.a1;
+}
+
+phys_size_t tfa_get_dram_size(void)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(SIP_SVC_GET_DDR_SIZE, -1, 0, 0, 0, 0, 0, 0, &res);
+ if (res.a0)
+ return 0;
+
+ return res.a1;
+}
+
+int tfa_get_board_number(void)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(SIP_SVC_GET_BOARD_NO, -1, 0, 0, 0, 0, 0, 0, &res);
+ if (res.a0)
+ return 0;
+
+ return res.a1;
+}
+
+phys_size_t tfa_get_sram_info(int ix, phys_addr_t *start)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(SIP_SVC_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+ if (res.a0 == 0 && res.a1 <= 1) {
+ /* SRAM info supported > 0.1 */
+ return 0;
+ }
+
+ arm_smccc_smc(SIP_SVC_SRAM_INFO, ix, 0, 0, 0, 0, 0, 0, &res);
+ if (res.a0) {
+ /* No SRAM segment 'ix' */
+ return 0;
+ }
+
+ /* Have SRAM segment */
+ *start = res.a1;
+ return res.a2;
+}
+
+__weak void reset_cpu(void)
+{
+ clrbits_le32(CPU_RESET_PROT_STAT, SYS_RST_PROT_VCORE_M);
+ setbits_le32(GCB_SOFT_RST, CHIP_SOFT_RST_M);
+}
+
+static char *part_id_string(u32 chip_id_reg)
+{
+ switch (FIELD_GET(PART_ID_M, chip_id_reg)) {
+ case LAN9691VAO:
+ return "LAN9691VAO";
+ case LAN9692VAO:
+ return "LAN9692VAO";
+ case LAN9693VAO:
+ return "LAN9693VAO";
+ case LAN9694:
+ return "LAN9694";
+ case LAN9694TSN:
+ return "LAN9694TSN";
+ case LAN9694RED:
+ return "LAN9694RED";
+ case LAN9696:
+ return "LAN9696";
+ case LAN9696TSN:
+ return "LAN9696TSN";
+ case LAN9696RED:
+ return "LAN9696RED";
+ case LAN9698:
+ return "LAN9698";
+ case LAN9698TSN:
+ return "LAN9698TSN";
+ case LAN9698RED:
+ return "LAN9698RED";
+ default:
+ return "Unknown ID";
+ }
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: %s\n", part_id_string(readl(GCB_CHIP_ID)));
+
+ return 0;
+}
diff --git a/board/microchip/lan969x/Makefile b/board/microchip/lan969x/Makefile
new file mode 100644
index 00000000000..97e3de097b4
--- /dev/null
+++ b/board/microchip/lan969x/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := lan969x.o
diff --git a/board/microchip/lan969x/lan969x.c b/board/microchip/lan969x/lan969x.c
new file mode 100644
index 00000000000..47083a95999
--- /dev/null
+++ b/board/microchip/lan969x/lan969x.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries.
+ */
+
+#include <asm/io.h>
+#include <asm/armv8/cpu.h>
+#include <asm/armv8/mmu.h>
+#include <dm/uclass.h>
+#include <dm/uclass-internal.h>
+#include <linux/sizes.h>
+#include <asm/global_data.h>
+#include <env.h>
+#include <env_internal.h>
+
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region fa_mem_map[] = {
+ {
+ .virt = PHYS_SDRAM_1,
+ .phys = PHYS_SDRAM_1,
+ .size = PHYS_SDRAM_1_SIZE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = LAN969X_SRAM_BASE,
+ .phys = LAN969X_SRAM_BASE,
+ .size = LAN969X_SRAM_SIZE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = LAN969X_QSPI0_MMAP,
+ .phys = LAN969X_QSPI0_MMAP,
+ .size = LAN969X_QSPI0_RANGE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = LAN969X_DEV_BASE,
+ .phys = LAN969X_DEV_BASE,
+ .size = LAN969X_DEV_SIZE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = LAN969X_USB_BASE,
+ .phys = LAN969X_USB_BASE,
+ .size = LAN969X_USB_SIZE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+struct mm_region *mem_map = fa_mem_map;
+
+int dram_init(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+
+ /* Fall-back to compile-time default */
+ if (!gd->ram_size)
+ gd->ram_size = LAN969X_DDR_SIZE_DEF;
+
+ return 0;
+}
+
+static void add_memory_bank(int bankno, phys_addr_t start, phys_size_t size)
+{
+ gd->bd->bi_dram[bankno].start = start;
+ gd->bd->bi_dram[bankno].size = size;
+}
+
+int dram_init_banksize(void)
+{
+ int bankno = 0;
+ phys_addr_t start;
+ phys_size_t size;
+
+ /* Add DDR */
+ add_memory_bank(bankno++, PHYS_SDRAM_1, gd->ram_size);
+
+ /* First the lower half of SRAM */
+ size = tfa_get_sram_info(0, &start);
+ if (size) {
+ add_memory_bank(bankno++, start, size);
+ }
+
+ /* Upper half of SRAM has 1st 128K reserved for BL31 */
+ size = tfa_get_sram_info(1, &start);
+ if (size) {
+ add_memory_bank(bankno++, start, size);
+ }
+
+ return 0;
+}
+
+int arch_cpu_init(void)
+{
+ return 0;
+}
+
+int mach_cpu_init(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
diff --git a/configs/microchip_ev23x71a_defconfig b/configs/microchip_ev23x71a_defconfig
new file mode 100644
index 00000000000..2717f6e9adf
--- /dev/null
+++ b/configs/microchip_ev23x71a_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+CONFIG_ARCH_MICROCHIPSW=y
+CONFIG_TFABOOT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_ENV_OFFSET=0x0
+CONFIG_DEFAULT_DEVICE_TREE="lan9696-ev23x71a"
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_SYS_LOAD_ADDR=0x64000000
+CONFIG_DEBUG_UART_BASE=0xe0040200
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
+CONFIG_HUSH_PARSER=y
+# CONFIG_HUSH_OLD_PARSER is not set
+CONFIG_HUSH_MODERN_PARSER=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_WGET=y
+CONFIG_EFI_PARTITION=y
+CONFIG_DEVICE_TREE_INCLUDES="lan969x-u-boot.dtsi"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_MMC_USE_SW_PARTITION=y
+CONFIG_ENV_MMC_SW_PARTITION="Env"
+CONFIG_PROT_TCP_SACK=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_CLK_LAN966X=y
+# CONFIG_I2C is not set
+# CONFIG_INPUT is not set
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_MICROCHIP_FLEXCOM=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_MICROCHIP=y
+CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
+CONFIG_MSCC_LAN969X_SWITCH=y
+CONFIG_MDIO_MSCC_MIIM=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_LAN969X=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_GPIO=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
diff --git a/include/configs/lan969x.h b/include/configs/lan969x.h
new file mode 100644
index 00000000000..3164b1b3da2
--- /dev/null
+++ b/include/configs/lan969x.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __LAN969X_CONFIG_H
+#define __LAN969X_CONFIG_H
+
+#include <linux/sizes.h>
+
+/* LAN969X defines */
+#define LAN969X_QSPI0_MMAP UL(0x20000000)
+#define LAN969X_QSPI0_RANGE SZ_256M
+#define LAN969X_SRAM_BASE UL(0x00100000)
+#define LAN969X_SRAM_SIZE SZ_2M
+#define LAN969X_DDR_BASE UL(0x60000000)
+#define LAN969X_DDR_SIZE_DEF (SZ_1G - (SZ_1G / 8)) /* ECC enabled cost 1/8th capacity */
+#define LAN969X_DDR_SIZE_MAX SZ_2G
+
+#define LAN969X_DEV_BASE UL(0xE0000000)
+#define LAN969X_DEV_SIZE UL(0x10000000)
+
+#define LAN969X_USB_BASE 0x300000
+#define LAN969X_USB_SIZE 0x80000
+
+#define PHYS_SDRAM_1 LAN969X_DDR_BASE
+#define PHYS_SDRAM_1_SIZE LAN969X_DDR_SIZE_MAX /* Used for MMU table - only */
+
+#define CFG_SYS_SDRAM_BASE LAN969X_DDR_BASE
+#define CFG_SYS_INIT_RAM_ADDR (LAN969X_DDR_BASE + SZ_64M)
+#define CFG_SYS_INIT_RAM_SIZE SZ_32K
+
+#define CFG_SYS_BOOTMAPSZ SZ_64M /* Initial map for Linux*/
+
+#endif /* __LAN969X_CONFIG_H */
--
2.53.0
More information about the U-Boot
mailing list