[PATCH v4 2/5] sunxi: h616: move PHY init tables into timing files
James Hilliard
james.hilliard1 at gmail.com
Fri Mar 27 21:09:13 CET 2026
Store the compile-time-selected PHY initialisation data alongside
each H616 timing implementation instead of in the common H616
DRAM code.
The common code still consumes a single phy_init pointer, so this
only moves the DRAM-type-specific data without changing the
selection model.
Signed-off-by: James Hilliard <james.hilliard1 at gmail.com>
---
.../include/asm/arch-sunxi/dram_sun50i_h616.h | 3 ++
arch/arm/mach-sunxi/dram_sun50i_h616.c | 41 +------------------
.../mach-sunxi/dram_timings/h616_ddr3_1333.c | 18 ++++++++
.../arm/mach-sunxi/dram_timings/h616_lpddr3.c | 18 ++++++++
.../dram_timings/h616_lpddr4_2133.c | 18 ++++++++
5 files changed, 58 insertions(+), 40 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
index c35ef0252cb..fa12d5d2685 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
@@ -168,6 +168,8 @@ struct dram_config {
u8 bus_full_width;
};
+#define H616_PHY_INIT_LEN 27
+
static inline int ns_to_t(const struct dram_para *para, int nanoseconds)
{
const unsigned int ctrl_freq = para->clk / 2;
@@ -175,6 +177,7 @@ static inline int ns_to_t(const struct dram_para *para, int nanoseconds)
return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
}
+extern const u8 *phy_init;
void mctl_set_timing_params(const struct dram_para *para);
#endif /* _SUNXI_DRAM_SUN50I_H616_H */
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 3345c9b8e82..5ee1ca25311 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -227,45 +227,6 @@ static void mctl_set_addrmap(const struct dram_config *config)
mctl_ctl->addrmap[8] = 0x3F3F;
}
-#ifdef CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_1
-static const u8 phy_init[] = {
-#ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333
- 0x08, 0x02, 0x12, 0x05, 0x15, 0x17, 0x18, 0x0b,
- 0x14, 0x07, 0x04, 0x13, 0x0c, 0x00, 0x16, 0x1a,
- 0x0a, 0x11, 0x03, 0x10, 0x0e, 0x01, 0x0d, 0x19,
- 0x06, 0x09, 0x0f
-#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR3)
- 0x18, 0x00, 0x04, 0x09, 0x06, 0x05, 0x02, 0x19,
- 0x17, 0x03, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07,
- 0x08, 0x01, 0x1a
-#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4)
- 0x03, 0x00, 0x17, 0x05, 0x02, 0x19, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01,
- 0x18, 0x04, 0x1a
-#endif
-};
-#else /* CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_0 */
-static const u8 phy_init[] = {
-#ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333
- 0x07, 0x0b, 0x02, 0x16, 0x0d, 0x0e, 0x14, 0x19,
- 0x0a, 0x15, 0x03, 0x13, 0x04, 0x0c, 0x10, 0x06,
- 0x0f, 0x11, 0x1a, 0x01, 0x12, 0x17, 0x00, 0x08,
- 0x09, 0x05, 0x18
-#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR3)
- 0x18, 0x06, 0x00, 0x05, 0x04, 0x03, 0x09, 0x02,
- 0x08, 0x01, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07,
- 0x17, 0x19, 0x1a
-#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4)
- 0x02, 0x00, 0x17, 0x05, 0x04, 0x19, 0x06, 0x07,
- 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01,
- 0x18, 0x03, 0x1a
-#endif
-};
-#endif /* CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_0 */
#define MASK_BYTE(reg, nr) (((reg) >> ((nr) * 8)) & 0x1f)
static void mctl_phy_configure_odt(const struct dram_para *para)
{
@@ -964,7 +925,7 @@ static bool mctl_phy_init(const struct dram_para *para,
writel(val2, SUNXI_DRAM_PHY0_BASE + 0x37c);
ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xc0);
- for (i = 0; i < ARRAY_SIZE(phy_init); i++)
+ for (i = 0; i < H616_PHY_INIT_LEN; i++)
writel(phy_init[i], &ptr[i]);
if (para->tpr10 & TPR10_CA_BIT_DELAY)
diff --git a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c
index 1f0d0de198c..f367f604d5f 100644
--- a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c
+++ b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c
@@ -14,6 +14,24 @@
#include <asm/arch/dram.h>
#include <asm/arch/cpu.h>
+static const u8 h616_ddr3_phy_init_default[H616_PHY_INIT_LEN] = {
+ 0x07, 0x0b, 0x02, 0x16, 0x0d, 0x0e, 0x14, 0x19,
+ 0x0a, 0x15, 0x03, 0x13, 0x04, 0x0c, 0x10, 0x06,
+ 0x0f, 0x11, 0x1a, 0x01, 0x12, 0x17, 0x00, 0x08,
+ 0x09, 0x05, 0x18
+};
+
+static const u8 h616_ddr3_phy_init_addr_map_1[H616_PHY_INIT_LEN] = {
+ 0x08, 0x02, 0x12, 0x05, 0x15, 0x17, 0x18, 0x0b,
+ 0x14, 0x07, 0x04, 0x13, 0x0c, 0x00, 0x16, 0x1a,
+ 0x0a, 0x11, 0x03, 0x10, 0x0e, 0x01, 0x0d, 0x19,
+ 0x06, 0x09, 0x0f
+};
+
+const u8 *phy_init = IS_ENABLED(CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_1) ?
+ h616_ddr3_phy_init_addr_map_1 :
+ h616_ddr3_phy_init_default;
+
void mctl_set_timing_params(const struct dram_para *para)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
diff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c
index e753fd7b4af..7efb1b22a84 100644
--- a/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c
+++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c
@@ -14,6 +14,24 @@
#include <asm/arch/dram.h>
#include <asm/arch/cpu.h>
+static const u8 h616_lpddr3_phy_init_default[H616_PHY_INIT_LEN] = {
+ 0x18, 0x06, 0x00, 0x05, 0x04, 0x03, 0x09, 0x02,
+ 0x08, 0x01, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07,
+ 0x17, 0x19, 0x1a
+};
+
+static const u8 h616_lpddr3_phy_init_addr_map_1[H616_PHY_INIT_LEN] = {
+ 0x18, 0x00, 0x04, 0x09, 0x06, 0x05, 0x02, 0x19,
+ 0x17, 0x03, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07,
+ 0x08, 0x01, 0x1a
+};
+
+const u8 *phy_init = IS_ENABLED(CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_1) ?
+ h616_lpddr3_phy_init_addr_map_1 :
+ h616_lpddr3_phy_init_default;
+
void mctl_set_timing_params(const struct dram_para *para)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
diff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c
index bbe401464eb..055d8dd3cad 100644
--- a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c
+++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c
@@ -12,6 +12,24 @@
#include <asm/arch/dram.h>
#include <asm/arch/cpu.h>
+static const u8 h616_lpddr4_phy_init_default[H616_PHY_INIT_LEN] = {
+ 0x02, 0x00, 0x17, 0x05, 0x04, 0x19, 0x06, 0x07,
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01,
+ 0x18, 0x03, 0x1a
+};
+
+static const u8 h616_lpddr4_phy_init_addr_map_1[H616_PHY_INIT_LEN] = {
+ 0x03, 0x00, 0x17, 0x05, 0x02, 0x19, 0x06, 0x07,
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01,
+ 0x18, 0x04, 0x1a
+};
+
+const u8 *phy_init = IS_ENABLED(CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_1) ?
+ h616_lpddr4_phy_init_addr_map_1 :
+ h616_lpddr4_phy_init_default;
+
void mctl_set_timing_params(const struct dram_para *para)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
--
2.43.0
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