[PATCH v6 1/7] riscv: Add initial support for P8700 SoC

[Yao Zi]

On Fri, Mar 27, 2026 at 02:11:15PM +0000, Uros Stajic wrote:
> From: Chao-ying Fu <cfu at mips.com>
> 
> Add initial platform support for the P8700-F, a high-performance
> multi-core RV64GC SoC with optional multi-cluster configuration and
> hardware multithreading.
> 
> This patch introduces the initial platform code necessary to support
> the P8700 CPU in U-Boot.
> 
> Signed-off-by: Chao-ying Fu <cfu at mips.com>
> Signed-off-by: Uros Stajic <uros.stajic at htecgroup.com>
> ---
>  arch/riscv/Kconfig                        |   8 ++
>  arch/riscv/cpu/p8700/Kconfig              |  14 +++
>  arch/riscv/cpu/p8700/Makefile             |   8 ++
>  arch/riscv/cpu/p8700/cache.c              |  93 +++++++++++++++++++
>  arch/riscv/cpu/p8700/cpu.c                | 105 ++++++++++++++++++++++
>  arch/riscv/cpu/p8700/dram.c               |  37 ++++++++
>  arch/riscv/cpu/p8700/p8700.c              |  12 +++
>  arch/riscv/include/asm/arch-p8700/p8700.h | 101 +++++++++++++++++++++
>  8 files changed, 378 insertions(+)
>  create mode 100644 arch/riscv/cpu/p8700/Kconfig
>  create mode 100644 arch/riscv/cpu/p8700/Makefile
>  create mode 100644 arch/riscv/cpu/p8700/cache.c
>  create mode 100644 arch/riscv/cpu/p8700/cpu.c
>  create mode 100644 arch/riscv/cpu/p8700/dram.c
>  create mode 100644 arch/riscv/cpu/p8700/p8700.c
>  create mode 100644 arch/riscv/include/asm/arch-p8700/p8700.h
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 79867656b15..9e2cbe775d2 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -132,6 +132,7 @@ source "arch/riscv/cpu/jh7110/Kconfig"
>  source "arch/riscv/cpu/k1/Kconfig"
>  source "arch/riscv/cpu/k230/Kconfig"
>  source "arch/riscv/cpu/th1520/Kconfig"
> +source "arch/riscv/cpu/p8700/Kconfig"
>  
>  # architecture-specific options below
>  
> @@ -442,6 +443,13 @@ config SBI
>  	bool
>  	default y if RISCV_SMODE || SPL_RISCV_SMODE
>  
> +config RISCV_CM_BASE
> +	hex "RISCV CM Base Address"
> +	default 0x16100000
> +	help
> +	  The physical base address at which to map the Coherence Manager
> +	  Global Configuration Registers (GCRs).
> +

Sorry for not raising this earlier: this sounds like a MIPS-specific
component, would it make sense to move it into a MIPS/P8700-specific
header? For example, arch/riscv/cpu/p8700/Kconfig.

>  choice
>  	prompt "SBI support"
>  	default SBI_V02

Regards,
Yao Zi