[PATCH v2 2/4] pinctrl: mediatek: mt8189: fix pinconf bias
David Lechner
dlechner at baylibre.com
Mon Mar 30 18:00:34 CEST 2026
Fix setting pinconf bias for MT8189.
Using mtk_pinconf_bias_set_v1() was wrong because MT8189 does not have
PULLEN/PULLSEL registers. It has PU and PD registers for most pins.
MSDC pins need special handling since they have PUPD/R1/R0 registers.
I2C pins need special handling since they have PU/PD/RSEL registers.
New groups are added for MSDC and I2C pins and the bias_set callback
is now set appropriately for all groups.
A new table is needed for the RSEL registers since those were missing.
Some new macros are introduced to avoid repeating the same info many
times in MTK_TYPED_PIN(). This also fixes the semantically incorrect
use of DRV_GRPX for the IO_TYPE_GRPX field.
Signed-off-by: David Lechner <dlechner at baylibre.com>
---
drivers/pinctrl/mediatek/pinctrl-mt8189.c | 413 +++++++++++++++++-------------
1 file changed, 229 insertions(+), 184 deletions(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8189.c b/drivers/pinctrl/mediatek/pinctrl-mt8189.c
index a64440d8bb3..9bcabe03151 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8189.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8189.c
@@ -1015,6 +1015,29 @@ static const struct mtk_pin_field_calc mt8189_pin_drv_range[] = {
PIN_FIELD_BASE(182, IO_BASE_RT, 0x0000, 9, 3),
};
+static const struct mtk_pin_field_calc mt8189_pin_rsel_range[] = {
+ PIN_FIELD_BASE(51, IO_BASE_RB1, 0x00B0, 0, 3), /* SCP_SCL0 */
+ PIN_FIELD_BASE(52, IO_BASE_RB1, 0x00B0, 6, 3), /* SCP_SDA0 */
+ PIN_FIELD_BASE(53, IO_BASE_RB1, 0x00B0, 3, 3), /* SCP_SCL1 */
+ PIN_FIELD_BASE(54, IO_BASE_RB1, 0x00B0, 9, 3), /* SCP_SDA1 */
+ PIN_FIELD_BASE(55, IO_BASE_LM, 0x00B0, 0, 3), /* SCL2 */
+ PIN_FIELD_BASE(56, IO_BASE_LM, 0x00B0, 3, 3), /* SDA2 */
+ PIN_FIELD_BASE(57, IO_BASE_BM1, 0x00B0, 0, 3), /* SCL3 */
+ PIN_FIELD_BASE(58, IO_BASE_BM1, 0x00B0, 12, 3), /* SDA3 */
+ PIN_FIELD_BASE(59, IO_BASE_BM1, 0x00B0, 3, 3), /* SCL4 */
+ PIN_FIELD_BASE(60, IO_BASE_BM1, 0x00B0, 15, 3), /* SDA4 */
+ PIN_FIELD_BASE(61, IO_BASE_BM1, 0x00B0, 6, 3), /* SCL5 */
+ PIN_FIELD_BASE(62, IO_BASE_BM1, 0x00B0, 18, 3), /* SDA5 */
+ PIN_FIELD_BASE(63, IO_BASE_BM1, 0x00B0, 9, 3), /* SCL6 */
+ PIN_FIELD_BASE(64, IO_BASE_BM1, 0x00B0, 21, 3), /* SDA6 */
+ PIN_FIELD_BASE(65, IO_BASE_RT, 0x00E0, 0, 3), /* SCL7 */
+ PIN_FIELD_BASE(66, IO_BASE_RT, 0x00E0, 6, 3), /* SDA7 */
+ PIN_FIELD_BASE(67, IO_BASE_RT, 0x00E0, 3, 3), /* SCL8 */
+ PIN_FIELD_BASE(68, IO_BASE_RT, 0x00E0, 9, 3), /* SDA8 */
+ PIN_FIELD_BASE(180, IO_BASE_LT0, 0x0110, 0, 3), /* SPMI_P_SCL */
+ PIN_FIELD_BASE(181, IO_BASE_LT0, 0x0110, 3, 3), /* SPMI_P_SDA */
+};
+
static const struct mtk_pin_reg_calc mt8189_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8189_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8189_pin_dir_range),
@@ -1028,6 +1051,7 @@ static const struct mtk_pin_reg_calc mt8189_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8189_pin_pu_range),
[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8189_pin_pd_range),
[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8189_pin_drv_range),
+ [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8189_pin_rsel_range),
};
static const char * const mt8189_pinctrl_register_base_names[] = {
@@ -1048,196 +1072,217 @@ static const char * const mt8189_pinctrl_register_base_names[] = {
[IO_BASE_EINT4] = "eint4",
};
+#define MT8189_TYPE0_PIN(_number, _name) \
+ MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0)
+
+#define MT8189_TYPE1_PIN(_number, _name) \
+ MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1)
+
+#define MT8189_TYPE2_PIN(_number, _name) \
+ MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP2)
+
static const struct mtk_pin_desc mt8189_pins[] = {
- MTK_TYPED_PIN(0, "GPIO00", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(1, "GPIO01", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(2, "GPIO02", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(3, "GPIO03", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(4, "GPIO04", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(5, "GPIO05", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(6, "GPIO06", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(7, "GPIO07", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(8, "GPIO08", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(9, "GPIO09", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(10, "GPIO10", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(11, "GPIO11", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(12, "GPIO12", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(13, "GPIO13", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(14, "GPIO14", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(15, "GPIO15", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(16, "GPIO16", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(17, "GPIO17", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(18, "GPIO18", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(19, "GPIO19", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(20, "GPIO20", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(21, "GPIO21", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(22, "GPIO22", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(23, "GPIO23", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(24, "GPIO24", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(25, "GPIO25", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(26, "GPIO26", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(27, "GPIO27", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(28, "GPIO28", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(29, "GPIO29", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(30, "GPIO30", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(31, "GPIO31", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(32, "GPIO32", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(33, "GPIO33", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(34, "GPIO34", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(35, "GPIO35", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(36, "GPIO36", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(37, "GPIO37", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(38, "GPIO38", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(39, "GPIO39", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(40, "GPIO40", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(41, "GPIO41", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(42, "GPIO42", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(43, "GPIO43", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(44, "GPIO44", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(45, "GPIO45", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(46, "GPIO46", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(47, "GPIO47", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(48, "GPIO48", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(49, "GPIO49", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(50, "GPIO50", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(51, "GPIO51", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(52, "GPIO52", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(53, "GPIO53", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(54, "GPIO54", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(55, "GPIO55", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(56, "GPIO56", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(57, "GPIO57", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(58, "GPIO58", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(59, "GPIO59", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(60, "GPIO60", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(61, "GPIO61", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(62, "GPIO62", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(63, "GPIO63", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(64, "GPIO64", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(65, "GPIO65", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(66, "GPIO66", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(67, "GPIO67", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(68, "GPIO68", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(69, "GPIO69", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(70, "GPIO70", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(71, "GPIO71", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(72, "GPIO72", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(73, "GPIO73", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(74, "GPIO74", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(75, "GPIO75", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(76, "GPIO76", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(77, "GPIO77", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(78, "GPIO78", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(79, "GPIO79", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(80, "GPIO80", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(81, "GPIO81", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(82, "GPIO82", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(83, "GPIO83", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(84, "GPIO84", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(85, "GPIO85", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(86, "GPIO86", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(87, "GPIO87", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(88, "GPIO88", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(89, "GPIO89", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(90, "GPIO90", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(91, "GPIO91", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(92, "GPIO92", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(93, "GPIO93", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(94, "GPIO94", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(95, "GPIO95", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(96, "GPIO96", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(97, "GPIO97", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(98, "GPIO98", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(99, "GPIO99", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(100, "GPIO100", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(101, "GPIO101", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(102, "GPIO102", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(103, "GPIO103", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(104, "GPIO104", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(105, "GPIO105", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(106, "GPIO106", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(107, "GPIO107", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(108, "GPIO108", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(109, "GPIO109", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(110, "GPIO110", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(111, "GPIO111", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(112, "GPIO112", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(113, "GPIO113", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(114, "GPIO114", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(115, "GPIO115", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(116, "GPIO116", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(117, "GPIO117", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(118, "GPIO118", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(119, "GPIO119", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(120, "GPIO120", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(121, "GPIO121", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(122, "GPIO122", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(123, "GPIO123", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(124, "GPIO124", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(125, "GPIO125", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(126, "GPIO126", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(127, "GPIO127", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(128, "GPIO128", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(129, "GPIO129", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(130, "GPIO130", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(131, "GPIO131", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(132, "GPIO132", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(133, "GPIO133", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(134, "GPIO134", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(135, "GPIO135", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(136, "GPIO136", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(137, "GPIO137", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(138, "GPIO138", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(139, "GPIO139", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(140, "GPIO140", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(141, "GPIO141", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(142, "GPIO142", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(143, "GPIO143", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(144, "GPIO144", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(145, "GPIO145", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(146, "GPIO146", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(147, "GPIO147", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(148, "GPIO148", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(149, "GPIO149", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(150, "GPIO150", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(151, "GPIO151", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(152, "GPIO152", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(153, "GPIO153", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(154, "GPIO154", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(155, "GPIO155", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(156, "GPIO156", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(157, "GPIO157", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(158, "GPIO158", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(159, "GPIO159", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(160, "GPIO160", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(161, "GPIO161", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(162, "GPIO162", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(163, "GPIO163", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(164, "GPIO164", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(165, "GPIO165", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(166, "GPIO166", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(167, "GPIO167", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(168, "GPIO168", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(169, "GPIO169", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(170, "GPIO170", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(171, "GPIO171", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(172, "GPIO172", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(173, "GPIO173", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(174, "GPIO174", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(175, "GPIO175", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(176, "GPIO176", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(177, "GPIO177", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(178, "GPIO178", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(179, "GPIO179", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(180, "GPIO180", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(181, "GPIO181", DRV_GRP4, DRV_GRP0),
- MTK_TYPED_PIN(182, "GPIO182", DRV_GRP4, DRV_GRP0),
+ MT8189_TYPE0_PIN(0, "GPIO00"),
+ MT8189_TYPE0_PIN(1, "GPIO01"),
+ MT8189_TYPE0_PIN(2, "GPIO02"),
+ MT8189_TYPE0_PIN(3, "GPIO03"),
+ MT8189_TYPE0_PIN(4, "GPIO04"),
+ MT8189_TYPE0_PIN(5, "GPIO05"),
+ MT8189_TYPE0_PIN(6, "GPIO06"),
+ MT8189_TYPE0_PIN(7, "GPIO07"),
+ MT8189_TYPE0_PIN(8, "GPIO08"),
+ MT8189_TYPE0_PIN(9, "GPIO09"),
+ MT8189_TYPE0_PIN(10, "GPIO10"),
+ MT8189_TYPE0_PIN(11, "GPIO11"),
+ MT8189_TYPE0_PIN(12, "GPIO12"),
+ MT8189_TYPE0_PIN(13, "GPIO13"),
+ MT8189_TYPE0_PIN(14, "GPIO14"),
+ MT8189_TYPE0_PIN(15, "GPIO15"),
+ MT8189_TYPE0_PIN(16, "GPIO16"),
+ MT8189_TYPE0_PIN(17, "GPIO17"),
+ MT8189_TYPE0_PIN(18, "GPIO18"),
+ MT8189_TYPE0_PIN(19, "GPIO19"),
+ MT8189_TYPE0_PIN(20, "GPIO20"),
+ MT8189_TYPE0_PIN(21, "GPIO21"),
+ MT8189_TYPE0_PIN(22, "GPIO22"),
+ MT8189_TYPE0_PIN(23, "GPIO23"),
+ MT8189_TYPE0_PIN(24, "GPIO24"),
+ MT8189_TYPE0_PIN(25, "GPIO25"),
+ MT8189_TYPE0_PIN(26, "GPIO26"),
+ MT8189_TYPE0_PIN(27, "GPIO27"),
+ MT8189_TYPE0_PIN(28, "GPIO28"),
+ MT8189_TYPE0_PIN(29, "GPIO29"),
+ MT8189_TYPE0_PIN(30, "GPIO30"),
+ MT8189_TYPE0_PIN(31, "GPIO31"),
+ MT8189_TYPE0_PIN(32, "GPIO32"),
+ MT8189_TYPE0_PIN(33, "GPIO33"),
+ MT8189_TYPE0_PIN(34, "GPIO34"),
+ MT8189_TYPE0_PIN(35, "GPIO35"),
+ MT8189_TYPE0_PIN(36, "GPIO36"),
+ MT8189_TYPE0_PIN(37, "GPIO37"),
+ MT8189_TYPE0_PIN(38, "GPIO38"),
+ MT8189_TYPE0_PIN(39, "GPIO39"),
+ MT8189_TYPE0_PIN(40, "GPIO40"),
+ MT8189_TYPE0_PIN(41, "GPIO41"),
+ MT8189_TYPE0_PIN(42, "GPIO42"),
+ MT8189_TYPE0_PIN(43, "GPIO43"),
+ MT8189_TYPE1_PIN(44, "GPIO44"),
+ MT8189_TYPE1_PIN(45, "GPIO45"),
+ MT8189_TYPE1_PIN(46, "GPIO46"),
+ MT8189_TYPE1_PIN(47, "GPIO47"),
+ MT8189_TYPE0_PIN(48, "GPIO48"),
+ MT8189_TYPE0_PIN(49, "GPIO49"),
+ MT8189_TYPE0_PIN(50, "GPIO50"),
+ MT8189_TYPE2_PIN(51, "GPIO51"),
+ MT8189_TYPE2_PIN(52, "GPIO52"),
+ MT8189_TYPE2_PIN(53, "GPIO53"),
+ MT8189_TYPE2_PIN(54, "GPIO54"),
+ MT8189_TYPE2_PIN(55, "GPIO55"),
+ MT8189_TYPE2_PIN(56, "GPIO56"),
+ MT8189_TYPE2_PIN(57, "GPIO57"),
+ MT8189_TYPE2_PIN(58, "GPIO58"),
+ MT8189_TYPE2_PIN(59, "GPIO59"),
+ MT8189_TYPE2_PIN(60, "GPIO60"),
+ MT8189_TYPE2_PIN(61, "GPIO61"),
+ MT8189_TYPE2_PIN(62, "GPIO62"),
+ MT8189_TYPE2_PIN(63, "GPIO63"),
+ MT8189_TYPE2_PIN(64, "GPIO64"),
+ MT8189_TYPE2_PIN(65, "GPIO65"),
+ MT8189_TYPE2_PIN(66, "GPIO66"),
+ MT8189_TYPE2_PIN(67, "GPIO67"),
+ MT8189_TYPE2_PIN(68, "GPIO68"),
+ MT8189_TYPE0_PIN(69, "GPIO69"),
+ MT8189_TYPE0_PIN(70, "GPIO70"),
+ MT8189_TYPE0_PIN(71, "GPIO71"),
+ MT8189_TYPE0_PIN(72, "GPIO72"),
+ MT8189_TYPE0_PIN(73, "GPIO73"),
+ MT8189_TYPE0_PIN(74, "GPIO74"),
+ MT8189_TYPE0_PIN(75, "GPIO75"),
+ MT8189_TYPE0_PIN(76, "GPIO76"),
+ MT8189_TYPE0_PIN(77, "GPIO77"),
+ MT8189_TYPE0_PIN(78, "GPIO78"),
+ MT8189_TYPE0_PIN(79, "GPIO79"),
+ MT8189_TYPE0_PIN(80, "GPIO80"),
+ MT8189_TYPE0_PIN(81, "GPIO81"),
+ MT8189_TYPE0_PIN(82, "GPIO82"),
+ MT8189_TYPE0_PIN(83, "GPIO83"),
+ MT8189_TYPE0_PIN(84, "GPIO84"),
+ MT8189_TYPE0_PIN(85, "GPIO85"),
+ MT8189_TYPE0_PIN(86, "GPIO86"),
+ MT8189_TYPE0_PIN(87, "GPIO87"),
+ MT8189_TYPE0_PIN(88, "GPIO88"),
+ MT8189_TYPE0_PIN(89, "GPIO89"),
+ MT8189_TYPE0_PIN(90, "GPIO90"),
+ MT8189_TYPE0_PIN(91, "GPIO91"),
+ MT8189_TYPE0_PIN(92, "GPIO92"),
+ MT8189_TYPE0_PIN(93, "GPIO93"),
+ MT8189_TYPE0_PIN(94, "GPIO94"),
+ MT8189_TYPE0_PIN(95, "GPIO95"),
+ MT8189_TYPE0_PIN(96, "GPIO96"),
+ MT8189_TYPE0_PIN(97, "GPIO97"),
+ MT8189_TYPE0_PIN(98, "GPIO98"),
+ MT8189_TYPE0_PIN(99, "GPIO99"),
+ MT8189_TYPE0_PIN(100, "GPIO100"),
+ MT8189_TYPE0_PIN(101, "GPIO101"),
+ MT8189_TYPE0_PIN(102, "GPIO102"),
+ MT8189_TYPE0_PIN(103, "GPIO103"),
+ MT8189_TYPE0_PIN(104, "GPIO104"),
+ MT8189_TYPE0_PIN(105, "GPIO105"),
+ MT8189_TYPE0_PIN(106, "GPIO106"),
+ MT8189_TYPE0_PIN(107, "GPIO107"),
+ MT8189_TYPE0_PIN(108, "GPIO108"),
+ MT8189_TYPE0_PIN(109, "GPIO109"),
+ MT8189_TYPE0_PIN(110, "GPIO110"),
+ MT8189_TYPE0_PIN(111, "GPIO111"),
+ MT8189_TYPE0_PIN(112, "GPIO112"),
+ MT8189_TYPE0_PIN(113, "GPIO113"),
+ MT8189_TYPE0_PIN(114, "GPIO114"),
+ MT8189_TYPE0_PIN(115, "GPIO115"),
+ MT8189_TYPE0_PIN(116, "GPIO116"),
+ MT8189_TYPE0_PIN(117, "GPIO117"),
+ MT8189_TYPE0_PIN(118, "GPIO118"),
+ MT8189_TYPE0_PIN(119, "GPIO119"),
+ MT8189_TYPE0_PIN(120, "GPIO120"),
+ MT8189_TYPE0_PIN(121, "GPIO121"),
+ MT8189_TYPE0_PIN(122, "GPIO122"),
+ MT8189_TYPE0_PIN(123, "GPIO123"),
+ MT8189_TYPE0_PIN(124, "GPIO124"),
+ MT8189_TYPE0_PIN(125, "GPIO125"),
+ MT8189_TYPE0_PIN(126, "GPIO126"),
+ MT8189_TYPE0_PIN(127, "GPIO127"),
+ MT8189_TYPE0_PIN(128, "GPIO128"),
+ MT8189_TYPE0_PIN(129, "GPIO129"),
+ MT8189_TYPE0_PIN(130, "GPIO130"),
+ MT8189_TYPE0_PIN(131, "GPIO131"),
+ MT8189_TYPE0_PIN(132, "GPIO132"),
+ MT8189_TYPE0_PIN(133, "GPIO133"),
+ MT8189_TYPE0_PIN(134, "GPIO134"),
+ MT8189_TYPE0_PIN(135, "GPIO135"),
+ MT8189_TYPE0_PIN(136, "GPIO136"),
+ MT8189_TYPE0_PIN(137, "GPIO137"),
+ MT8189_TYPE0_PIN(138, "GPIO138"),
+ MT8189_TYPE0_PIN(139, "GPIO139"),
+ MT8189_TYPE0_PIN(140, "GPIO140"),
+ MT8189_TYPE0_PIN(141, "GPIO141"),
+ MT8189_TYPE0_PIN(142, "GPIO142"),
+ MT8189_TYPE0_PIN(143, "GPIO143"),
+ MT8189_TYPE0_PIN(144, "GPIO144"),
+ MT8189_TYPE0_PIN(145, "GPIO145"),
+ MT8189_TYPE0_PIN(146, "GPIO146"),
+ MT8189_TYPE0_PIN(147, "GPIO147"),
+ MT8189_TYPE0_PIN(148, "GPIO148"),
+ MT8189_TYPE0_PIN(149, "GPIO149"),
+ MT8189_TYPE0_PIN(150, "GPIO150"),
+ MT8189_TYPE0_PIN(151, "GPIO151"),
+ MT8189_TYPE0_PIN(152, "GPIO152"),
+ MT8189_TYPE0_PIN(153, "GPIO153"),
+ MT8189_TYPE0_PIN(154, "GPIO154"),
+ MT8189_TYPE0_PIN(155, "GPIO155"),
+ MT8189_TYPE1_PIN(156, "GPIO156"),
+ MT8189_TYPE1_PIN(157, "GPIO157"),
+ MT8189_TYPE1_PIN(158, "GPIO158"),
+ MT8189_TYPE1_PIN(159, "GPIO159"),
+ MT8189_TYPE1_PIN(160, "GPIO160"),
+ MT8189_TYPE1_PIN(161, "GPIO161"),
+ MT8189_TYPE1_PIN(162, "GPIO162"),
+ MT8189_TYPE1_PIN(163, "GPIO163"),
+ MT8189_TYPE1_PIN(164, "GPIO164"),
+ MT8189_TYPE1_PIN(165, "GPIO165"),
+ MT8189_TYPE1_PIN(166, "GPIO166"),
+ MT8189_TYPE1_PIN(167, "GPIO167"),
+ MT8189_TYPE1_PIN(168, "GPIO168"),
+ MT8189_TYPE1_PIN(169, "GPIO169"),
+ MT8189_TYPE1_PIN(170, "GPIO170"),
+ MT8189_TYPE1_PIN(171, "GPIO171"),
+ MT8189_TYPE1_PIN(172, "GPIO172"),
+ MT8189_TYPE1_PIN(173, "GPIO173"),
+ MT8189_TYPE1_PIN(174, "GPIO174"),
+ MT8189_TYPE1_PIN(175, "GPIO175"),
+ MT8189_TYPE1_PIN(176, "GPIO176"),
+ MT8189_TYPE1_PIN(177, "GPIO177"),
+ MT8189_TYPE1_PIN(178, "GPIO178"),
+ MT8189_TYPE1_PIN(179, "GPIO179"),
+ MT8189_TYPE2_PIN(180, "GPIO180"),
+ MT8189_TYPE2_PIN(181, "GPIO181"),
+ MT8189_TYPE0_PIN(182, "GPIO182"),
};
static const struct mtk_io_type_desc mt8189_io_type_desc[] = {
[IO_TYPE_GRP0] = {
.name = "mt8189",
- .bias_set = mtk_pinconf_bias_set_v1,
+ .bias_set = mtk_pinconf_bias_set_pu_pd,
+ .drive_set = mtk_pinconf_drive_set_v1,
+ .input_enable = mtk_pinconf_input_enable_v1,
+ },
+ [IO_TYPE_GRP1] = {
+ .name = "MSDC",
+ .bias_set = mtk_pinconf_bias_set_pupd_r1_r0,
+ .drive_set = mtk_pinconf_drive_set_v1,
+ .input_enable = mtk_pinconf_input_enable_v1,
+ },
+ [IO_TYPE_GRP2] = {
+ .name = "I2C",
+ .bias_set = mtk_pinconf_bias_set_pu_pd_rsel,
.drive_set = mtk_pinconf_drive_set_v1,
.input_enable = mtk_pinconf_input_enable_v1,
},
--
2.43.0
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