[PATCH v2 1/3] arm: socfpga: Consolidate dram_bank_mmu_setup()

[Sune Brian]

Hi Tien Fong,

Disregarding to the code issue:
I am curious that aren't someone do mentioned the:

- Per-version change history must be placed below the '---' separator.
- The required format is 'Changes in vN:'.

???

So suddenly all these high standards immediately disappeared from one
patch to another patch?
Interesting =]

Thanks,
Brian

On Tue, May 5, 2026 at 1:03 PM Chee, Tien Fong
<tien.fong.chee at altera.com> wrote:
>
> Hi Alif,
>
>
> On 28/4/2026 11:32 am, alif.zakuan.yuslaimi at altera.com wrote:
> > From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
> >
> > Relocate the dram_bank_mmu_setup() implementation from misc_arria10.c to
> > the common socfpga misc.c and update the function to correctly handle both
> > pre-relocation and post-relocation cases for DRAM cache enabling for
> > consistent MMU/dcache setup across Arria10 and CycloneV platforms.
> >
> > These changes help to improve maintainability and consistency of DRAM
> > initialization as well as MMU configuration for Arria10 and CycloneV
> > platforms.
> >
> > New Kconfig is introduced to enable this implementation only on the default
> > Arria10 and CycloneV boards as this will increase the SPL size which
> > will exceed some Gen5 devices' SPL size limit.
> >
> > Fixes: e26ecebc684b ("socfpga: arria10: Allow dcache_enable before relocation")
> >
> > Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
> > ---
> >   arch/arm/mach-socfpga/Kconfig        |  1 +
> >   arch/arm/mach-socfpga/misc.c         | 31 ++++++++++++++++++++++++++++
> >   arch/arm/mach-socfpga/misc_arria10.c | 26 -----------------------
> >   3 files changed, 32 insertions(+), 26 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> > index fb98b647442..e2fdd6bb30f 100644
> > --- a/arch/arm/mach-socfpga/Kconfig
> > +++ b/arch/arm/mach-socfpga/Kconfig
> > @@ -115,6 +115,7 @@ config ARCH_SOCFPGA_CYCLONE5
> >   config ARCH_SOCFPGA_GEN5
> >       bool
> >       select SPL_ALTERA_SDRAM
> > +     select SPL_CACHE if SPL
>
>