[PATCH v2 1/3] arm: socfpga: Consolidate dram_bank_mmu_setup()

[Yuslaimi, Alif Zakuan]

Hi Tien Fong,

On 5/5/2026 1:03 pm, Chee, Tien Fong wrote:
> Hi Alif,
> 
> 
> On 28/4/2026 11:32 am, alif.zakuan.yuslaimi at altera.com wrote:
>> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
>>
>> Relocate the dram_bank_mmu_setup() implementation from misc_arria10.c to
>> the common socfpga misc.c and update the function to correctly handle 
>> both
>> pre-relocation and post-relocation cases for DRAM cache enabling for
>> consistent MMU/dcache setup across Arria10 and CycloneV platforms.
>>
>> These changes help to improve maintainability and consistency of DRAM
>> initialization as well as MMU configuration for Arria10 and CycloneV
>> platforms.
>>
>> New Kconfig is introduced to enable this implementation only on the 
>> default
>> Arria10 and CycloneV boards as this will increase the SPL size which
>> will exceed some Gen5 devices' SPL size limit.
>>
>> Fixes: e26ecebc684b ("socfpga: arria10: Allow dcache_enable before 
>> relocation")
>>
>> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
>> ---
>>   arch/arm/mach-socfpga/Kconfig        |  1 +
>>   arch/arm/mach-socfpga/misc.c         | 31 ++++++++++++++++++++++++++++
>>   arch/arm/mach-socfpga/misc_arria10.c | 26 -----------------------
>>   3 files changed, 32 insertions(+), 26 deletions(-)
>>
>> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/ 
>> Kconfig
>> index fb98b647442..e2fdd6bb30f 100644
>> --- a/arch/arm/mach-socfpga/Kconfig
>> +++ b/arch/arm/mach-socfpga/Kconfig
>> @@ -115,6 +115,7 @@ config ARCH_SOCFPGA_CYCLONE5
>>   config ARCH_SOCFPGA_GEN5
>>       bool
>>       select SPL_ALTERA_SDRAM
>> +    select SPL_CACHE if SPL
> 
> 
> Concern: Two-step SPL_CACHE Kconfig creates dangerous intermediate 
> bisect state
> 
> Impact:
> 
> Bisect or backport landing only patch 1 forces SPL_CACHE=y for 
> TARGET_SOCFPGA_TERASIC_SOCKIT,
> 
> TARGET_SOCFPGA_EBV_SOCRATES, TARGET_SOCFPGA_SOFTING_VINING_FPGA. SPL 
> exceeds 64 KiB limit and fails to boot.
> 
> Fix:
> 
> Remove the 'select SPL_CACHE if SPL' hunk from patch 1 entirely.
> 
> Add the correct conditional form 'select SPL_CACHE if SPL && 
> SOCFPGA_ECC_SUPPORT' only in patch 3 alongside SOCFPGA_ECC_SUPPORT.
> 
> Best regards,
> 
> Tien Fong
> 
Thank you for your input. I will address this in v3.

Alif