[PATCH v2 3/3] ddr: socfpga: Add ECC DRAM scrubbing support for Gen5/Arria10

[Yuslaimi, Alif Zakuan]

Hi Marek,

On 7/5/2026 11:51 am, Marek Vasut wrote:
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> 
> On 5/5/26 8:54 AM, Chee, Tien Fong wrote:
>> Hi Alif,
>>
>>
>> On 28/4/2026 11:32 am, alif.zakuan.yuslaimi at altera.com wrote:
>>> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
>>>
>>> The SDRAM must first be rewritten by zeroes if ECC is used to initialize
>>> the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a
>>> case.
>>>
>>> This implementation turns the caches on temporarily, then overwrites the
>>> whole RAM with zeroes, flushes the caches and turns them off again.
>>> This provides satisfactory performance.
>>>
>>> Move common code sdram_init_ecc_bits() to new common file sdram_soc32.c.
>>> Preparation for Gen5 uses the same memory initialization function as
>>> Arria10.
>>>
>>> New Kconfig is introduced to enable this implementation only on the
>>> default
>>> Arria10 and CycloneV boards as this will increase the SPL size which
>>> will exceed some Gen5 devices' SPL size limit.
> The subject is severely misleading, the ECC scrubbing was upstream since
> 2018:
> 
> 07252f6f7e37 ("ddr: altera: Add ECC DRAM scrubbing support for Arria10")
> 
>      ddr: altera: Add ECC DRAM scrubbing support for Arria10
> 
>      The SDRAM must first be rewritten by zeroes if ECC is used to
> initialize
>      the ECC metadata. Make the CPU overwrite the DRAM with zeroes in 
> such a
>      case. This scrubbing implementation turns the caches on
> temporarily, then
>      overwrites the whole RAM with zeroes, flushes the caches and turns 
> them
>      off again. This provides satisfactory performance.
> 
> Even the commit message of this patch is a duplicate of that one in the
> commit from 2018 ? What is going on here ?

This patch was derived from the original commit you have mentioned.

The intention of this patch is to bring over the ECC scrubbing support 
to Gen5 as well via a new common DDR driver shared by both Arria10 and 
Gen5 devices which is sdram_soc32.c. This makes ECC scrubbing support no 
longer exclusive only to Arria10.

Perhaps staying close to the original patch subject and message to 
describe the original functionality might have create some confusion 
here. I can rephrase the subject and the commit message for v3.

Do let me know if you have any suggestions for me to improve the commit 
message for the next submission, I can add your sign-off as well with 
your permission as you are the original author for this feature for Arria10.

Thanks,
Alif