[PATCH RFC 05/18] ram: rockchip: Update ddr pctl regs for px30

[Pavel Golikov]

Add RK3568 specific bits.

Signed-off-by: Pavel Golikov <paullo612 at ya.ru>
---
 .../include/asm/arch-rockchip/sdram_pctl_px30.h    | 26 ++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h b/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h
index 3780dc6ea5b..62ea55df744 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h
@@ -37,6 +37,7 @@ struct ddr_pctl_regs {
 #define DDR_PCTL2_RFSHTMG		0x64
 #define DDR_PCTL2_RFSHTMG1		0x68
 #define DDR_PCTL2_RFSHCTL5		0x6c
+#define DDR_PCTL2_ECCCFG0		0x70
 #define DDR_PCTL2_INIT0			0xd0
 #define DDR_PCTL2_INIT1			0xd4
 #define DDR_PCTL2_INIT2			0xd8
@@ -127,10 +128,15 @@ struct ddr_pctl_regs {
 	((0x1000 * (n) + (((n) > 0) ? 0x1000 : 0)))
 
 /* PCTL2_MSTR */
-#define PCTL2_FREQUENCY_MODE_MASK	(1)
-#define PCTL2_FREQUENCY_MODE_SHIFT	(29)
+#define PCTL2_FREQUENCY_MODE_FREQ1	BIT(29)
 #define PCTL2_DLL_OFF_MODE		BIT(15)
 /* PCTL2_STAT */
+#define PCTL2_SELFREF_STATE_MASK	(3 << 8)
+#define PCTL2_SELFREF_STATE_SHIFT	(8)
+#define PCTL2_SELFREF_STATE_IDLE	(0)
+#define PCTL2_SELFREF_STATE_SR1		(1)
+#define PCTL2_SELFREF_STATE_SR_PD	(2)
+#define PCTL2_SELFREF_STATE_SR2		(3)
 #define PCTL2_SELFREF_TYPE_MASK		(3 << 4)
 #define PCTL2_SELFREF_TYPE_SR_NOT_AUTO	(2 << 4)
 #define PCTL2_OPERATING_MODE_MASK	(7)
@@ -150,8 +156,11 @@ struct ddr_pctl_regs {
 /* PCTL2_MRSTAT */
 #define PCTL2_MR_WR_BUSY		BIT(0)
 /* PCTL2_DERATEEN */
+#define PCTL2_DERATE_MR4_PAUSE_FC	BIT(13)
+#define PCTL2_DERATE_MR4_TUF_DIS	BIT(12)
 #define PCTL2_DERATE_ENABLE		(1)
 /* PCTL2_PWRCTL */
+#define PCTL2_STAY_IN_SELFREF		BIT(6)
 #define PCTL2_SELFREF_SW		BIT(5)
 #define PCTL2_POWERDOWN_EN		BIT(1)
 #define PCTL2_SELFREF_EN		(1)
@@ -159,6 +168,12 @@ struct ddr_pctl_regs {
 #define PCTL2_SELFREF_TO_X32_MASK	(0xFF)
 #define PCTL2_SELFREF_TO_X32_SHIFT	(16)
 #define PCTL2_POWERDOWN_TO_X32_MASK	(0x1F)
+/* PCTL2_ECCCFG0*/
+#define PCTL2_ECC_MODE_MASK		(7)
+#define PCTL2_ECC_MODE_SHIFT		(0)
+#define PCTL2_ECC_MODE_DIS		(0)
+#define PCTL2_ECC_MODE_EN		(4)
+#define PCTL2_ECC_MODE_EN_ADVANCED	(5)
 /* PCTL2_INIT3 */
 #define PCTL2_DDR34_MR0_SHIFT		(16)
 #define PCTL2_LPDDR234_MR1_SHIFT	(16)
@@ -183,11 +198,16 @@ struct ddr_pctl_regs {
 
 #define PCTL2_MR_MASK			(0xffff)
 
+/* PCTL2_RANKCTL */
+#define PCTL2_DIFF_RANK_WR_GAP_SHIFT	(8)
+#define PCTL2_DIFF_RANK_WR_GAP_MASK	(0xf << 8)
+
 /* PCTL2_RFSHCTL3 */
 #define PCTL2_DIS_AUTO_REFRESH		(1)
 /* PCTL2_ZQCTL0 */
 #define PCTL2_DIS_AUTO_ZQ		BIT(31)
 #define PCTL2_DIS_SRX_ZQCL		BIT(30)
+#define PCTL2_ZQ_RESISTOR_SHARED	BIT(29)
 /* PCTL2_DFILPCFG0 */
 #define PCTL2_DFI_LP_EN_SR		BIT(8)
 #define PCTL2_DFI_LP_EN_SR_MASK		BIT(8)
@@ -197,6 +217,8 @@ struct ddr_pctl_regs {
 /* PCTL2_DFISTAT */
 #define PCTL2_DFI_LP_ACK		BIT(1)
 #define PCTL2_DFI_INIT_COMPLETE		(1)
+/* DDR_PCTL2_SCHED */
+#define PCTL2_PAGECLOSE_EN		BIT(2)
 /* PCTL2_DBG1 */
 #define PCTL2_DIS_HIF			BIT(1)
 /* PCTL2_DBGCAM */

-- 
2.25.1