[PATCH RFC 04/18] rockchip: rk3568: syscon: Add MSCH, SGRF and DDRGRF support

[Jonas Karlman]

Hi Pavel,

On 5/17/2026 9:24 PM, Pavel Golikov wrote:
> Add support for the MSCH, SGRF and DDRGRF register regions in syscon,
> which are necessary for RK3568's DRAM controller initialization.
> 
> Signed-off-by: Pavel Golikov <paullo612 at ya.ru>
> ---
>  arch/arm/include/asm/arch-rockchip/clock.h    |  1 +
>  arch/arm/mach-rockchip/rk3568/syscon_rk3568.c | 26 +++++++++++++++++++++++++-
>  2 files changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
> index 95b08bfd046..a6b399da4ff 100644
> --- a/arch/arm/include/asm/arch-rockchip/clock.h
> +++ b/arch/arm/include/asm/arch-rockchip/clock.h
> @@ -39,6 +39,7 @@ enum {
>  	ROCKCHIP_SYSCON_PIPE_PHY2_GRF,
>  	ROCKCHIP_SYSCON_VOP_GRF,
>  	ROCKCHIP_SYSCON_VO_GRF,
> +	ROCKCHIP_SYSCON_DDRGRF,
>  };
>  
>  /* Standard Rockchip clock numbers */
> diff --git a/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c b/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c
> index b9d59a4721e..7f6caf9ca67 100644
> --- a/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c
> +++ b/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c
> @@ -8,8 +8,11 @@
>  #include <asm/arch-rockchip/clock.h>
>  
>  static const struct udevice_id rk3568_syscon_ids[] = {
> -	{ .compatible = "rockchip,rk3568-grf", .data = ROCKCHIP_SYSCON_GRF },
> +	{ .compatible = "rockchip,rk3568-grf",    .data = ROCKCHIP_SYSCON_GRF    },
>  	{ .compatible = "rockchip,rk3568-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF },
> +	{ .compatible = "rockchip,rk3568-msch",   .data = ROCKCHIP_SYSCON_MSCH   },
> +	{ .compatible = "rockchip,rk3568-sgrf",   .data = ROCKCHIP_SYSCON_SGRF   },
> +	{ .compatible = "rockchip,rk3568-ddrgrf", .data = ROCKCHIP_SYSCON_DDRGRF },

Please do not add more mappings, all ROCKCHIP_SYSCON usage should
instead be removed. See [1] and [2] for some uncompleted work.

Please define constants instead of trying to do dynamic lookup. Drivers
that typically need to know these reg addresses are already specific for
a single SoC or needs to be known at compile-time to save space.

No need to waste cpu cycles at runtime trying to resolve them :-)

[1] https://source.denx.de/u-boot/contributors/kwiboo/u-boot/-/commits/optimize
[2] https://source.denx.de/u-boot/contributors/kwiboo/u-boot/-/commit/d1601adc6b0bb092b66863e0c515dda5746c6f6f

Regards,
Jonas

>  	{ }
>  };
>  
> @@ -37,4 +40,25 @@ U_BOOT_DRIVER(rockchip_rk3568_pmugrf) = {
>  	.of_match = rk3568_syscon_ids + 1,
>  	.bind = rk3568_syscon_bind_of_plat,
>  };
> +
> +U_BOOT_DRIVER(rockchip_rk3568_msch) = {
> +	.name = "rockchip_rk3568_msch",
> +	.id = UCLASS_SYSCON,
> +	.of_match = rk3568_syscon_ids + 2,
> +	.bind = rk3568_syscon_bind_of_plat,
> +};
> +
> +U_BOOT_DRIVER(rockchip_rk3568_sgrf) = {
> +	.name = "rockchip_rk3568_sgrf",
> +	.id = UCLASS_SYSCON,
> +	.of_match = rk3568_syscon_ids + 3,
> +	.bind = rk3568_syscon_bind_of_plat,
> +};
> +
> +U_BOOT_DRIVER(rockchip_rk3568_ddrgrf) = {
> +	.name = "rockchip_rk3568_ddrgrf",
> +	.id = UCLASS_SYSCON,
> +	.of_match = rk3568_syscon_ids + 4,
> +	.bind = rk3568_syscon_bind_of_plat,
> +};
>  #endif
>