[GIT PULL] amd/xilinx patches for v2025.07-rc3

[Michal Simek]

Hi Tom,

please pull these two fixes to your branch.

Thanks,
Michal

The following changes since commit 987c93fc68a641cc735c9828872511a947e54191:

   Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh 
(2026-05-22 13:30:42 -0600)

are available in the Git repository at:

   https://source.denx.de/u-boot/custodians/u-boot-microblaze.git 
tags/xilinx-for-v2026.07-rc3

for you to fetch changes up to 8a5989acc6ff1430a2775178d2e6b0b5d4573247:

   arm64: versal2: Fix buffer overflow in soc_name_decode (2026-05-25 15:14:05 
+0200)

----------------------------------------------------------------
AMD/Xilinx/FPGA changes for v2026.07-rc3

versal/fpga:
- Fix unaligned buffer handling

versal2:
- Fix buffer overflow in SOC name array

----------------------------------------------------------------
Francois Berder (1):
       arm64: versal2: Fix buffer overflow in soc_name_decode

Pranav Tilak (1):
       fpga: versalpl: Fix unaligned buffer handling

  board/amd/versal2/board.c | 9 +++++----
  drivers/fpga/versalpl.c   | 2 +-
  2 files changed, 6 insertions(+), 5 deletions(-)

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs
TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs