[U-Boot] [PATCH v2 00/16] sunxi: Allwinner A10/A13/A20 DRAM controller fixes

[Siarhei Siamashka]

This is version 2 of
    http://lists.denx.de/pipermail/u-boot/2014-July/183981.html

Rebased on git://git.denx.de/u-boot-sunxi.git master branch (commit
3340eab26d89176dd0bf543e6d2590665c577423 "sun7i: Add bananapi board")

Siarhei Siamashka (16):
  sunxi: dram: Remove useless 'dramc_scan_dll_para()' function
  sunxi: dram: Remove broken super-standby remnants
  sunxi: dram: Respect the DDR3 reset timing requirements
  sunxi: dram: Fix CKE delay handling for sun4i/sun5i
  sunxi: dram: Remove broken impedance and ODT configuration code
  sunxi: dram: Do DDR3 reset in the same way on sun4i/sun5i/sun7i
  sunxi: dram: Add 'await_bits_clear'/'await_bits_set' helper functions
  sunxi: dram: Re-introduce the impedance calibration ond ODT
  sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6)
  sunxi: dram: Use divisor P=1 for PLL5
  sunxi: dram: Improve DQS gate data training error handling
  sunxi: dram: Add a helper function 'mctl_get_number_of_lanes'
  sunxi: dram: Configurable DQS gating window mode and delay
  sunxi: dram: Drop DDR2 support and assume only single rank DDR3 memory
  sunxi: dram: Derive write recovery delay from DRAM clock speed
  sunxi: dram: Autodetect DDR3 bus width and density

 arch/arm/cpu/armv7/sunxi/dram.c        | 621 ++++++++++++++++++---------------
 arch/arm/include/asm/arch-sunxi/dram.h |  14 +-
 2 files changed, 351 insertions(+), 284 deletions(-)

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