[U-Boot-Users] Re: Interrupt management under PPC4xx platform
stefan.roese at esd-electronics.com
Mon Apr 14 15:42:15 CEST 2003
The EVPR is set to zero by U-Boot since the interrupts (exceptions) are
enabled when U-Boot is running from SDRAM and _not_ from flash anymore
(Wolfgang, please correct me, if I am wrong here). The exception vectors are
located (relocated) at addresses 0x100, 0x200, etc. The offset (EVPR) is
zero at this moment.
The interrupt management for PPC4xx in U-Boot is OK! We have several
different boards with IBM PPC's (PPC405CR, PPC405GP, PPC405GPr) running
without any problems here (timer and ethernet interrupts working).
Are you sure, that the interrupts are causing this "unstable" behaviour? I
would suspect, that other exceptions are responsible for this errors?
> Just after posting the message "Interrupt management under PPC4xx
> platform", I noticed the thread "405Gpr timer interrupt" describing the
> same problem I encountered with the Ethernet interface (I work with the
> 405EP eval. board). I think it is due to the incorrect interrupt
> management, too. For this reason, and since this is my first experience
> with U-Boot, I posted the message "Interrupt management under PPC4xx
> I got a more stable situation by intializing the EVPR register like this:
> #if 1
> /* OpenBIOS' way */
> addis r4,r0,CFG_MONITOR_BASE at h /*! set exception vector
> prefix */
> mtevpr r4 /*! to high ROM address */
> /* U-Boot's way */
> mtevpr r4
> but unfortunately I still have the problem with the Ethernet interface.
> Did you figure out what is wrong?
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