[U-Boot-Users] Can't get ide to work

Jerry Walden jerry.walden at lantronix.com
Thu Feb 5 01:13:09 CET 2004


Okay - got it!  My IDE interface (dbau1500) is at 0xf80000000 (pays to
read the data sheet) - so I just mapped TLB 22 to phy 0xf80000000 and it
works just dandy.

Thanks!

-----Original Message-----
From: Thomas Lange [mailto:thomas at corelatus.se] 
Sent: Wednesday, February 04, 2004 10:51 AM
To: Jerry Walden
Cc: u-boot-users at lists.sourceforge.net
Subject: Re: [U-Boot-Users] Can't get ide to work


tlb 20 is mapped to phy 0xF00000000 ( not used )
tlb 21 is mapped to phy 0xF40000000 ( not used )
tlb 22 is mapped to phy 0xF80000000

TLB 22 was enough to make CF work on my dbau1000 board
( only tested in big endian mode ).

/Thomas

Jerry Walden wrote:
> Thanks for the response.
> 
> Okay - I found the TLB mapping for CFG_PCMCIA_MEM_ADDR (0x20000000), 
> however the IDE device is at AU1X_SOCK0_IO (0xF00000000).  True - the 
> PCMCIA is at 0x20000000, however not the ide device.  If I look at the

> YAMON source - there is a mapping done for 0xF00000000.
> 
> I don't see it in u-boot.  Where am I going wrong?
> 
> Thanks
> 
> -----Original Message-----
> From: Thomas Lange [mailto:thomas at corelatus.se]
> Sent: Tuesday, February 03, 2004 1:29 PM
> To: Jerry Walden
> Cc: u-boot-users at lists.sourceforge.net
> Subject: Re: [U-Boot-Users] Can't get ide to work
> 
> 
> TLB is created in board/dbau1x00/dbau1x00.c
> 
> Could be an endian problem, i.e. you read the wrong byte.
> 
> /Thomas
> 
> Jerry Walden wrote:
> 
>>Our board is based on the Alchemy DBAu1500
>>
>>We are using a compact flash card that as an IDE drive (tied into the
>>IDE interface of the CPU just like the DBAu1500).
>>
>>During ide_init, the ATA_STATUS byte is read, and there is a wait loop
> 
> 
>>which waits for the status to be ready.  This loop always times out.
>>I am trying to debug this.  Tracing through ide_inb, and ide_outb, the
> 
> 
>>address of the interface is fine CFG_PCMCIA_MEM_ADDR (0x20000000).  I
>>know that there has to be some TLB mapping between CFG_PCMCIA_MEM_ADDR
> 
> 
>>(0x20000000) and AU1X_SOCK0_IO
>>(F00000000) - I just cannot find where this is done.
>>
>>Any suggestions?
>>
>>Thanks
> 
> 
> 
> 
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