[U-Boot-Users] PCI initialization in U-Boot

[Paul Wujek]

When U-Boot initializes a PCI board are all the
PCI memory regions properly assigned and ready
for use?

I am testing an IceCube/MPC5200 motherboard together
with a Diamond Stealth ATI Radeon 9200SE PCI card.

In drivers/pci_auto.c the function pciauto_setup_device looks
like it is setting up the memory regions.

I can access BAR1 (I/O region), and BAR2 (memory region),
although I haven't verified that I am looking at
the right memory.

Attempting to access BAR0 (memory region), results in a 'bus fault'.

I am writing a standalone application and my initial development
must use these boards, unfortunately I can't use an OS to set
PCI up properly.

Are there further configuration commands that must be executed
to access the BAR0 memory region?

Alternately, is there a source of information that I can read
to learn how to set up PCI so that my standalone application
can use it?


Here's example output that illustrates  my problem:
===================================================

U-Boot 1.1.1 (Oct 29 2004 - 08:46:47)

CPU:   MPC5200 (JTAG ID 0001101d) at 396 MHz
       Bus 132 MHz, IPB 66 MHz, PCI 33 MHz
Board: Motorola MPC5200 (IceCube)
I2C:   85 kHz, ready
DRAM:  64 MB
FLASH: 16 MB
PCI:   Bus Dev VenId DevId Class Int
        00  18  1002  5964  0300  ff
        00  18  1002  5d44  0380  ff
        00  1a  1057  5803  0680  00
In:    serial
Out:   serial
Err:   serial
Net:   FEC ETHERNET
IDE:   Bus 0: not available

Autostarting. Press any key to abort...

Hit any key to stop autoboot:  0
=> pci header 00.18.00
  vendor ID =                   0x1002
  device ID =                   0x5964
  command register =            0x0007
  status register =             0x0290
  revision ID =                 0x01
  class code =                  0x03 (Display controller)
  sub class code =              0x00
  programming interface =       0x00
  cache line =                  0x08
  latency time =                0x80
  header type =                 0x80
  BIST =                        0x00
  base address 0 =              0x40000008
  base address 1 =              0x50000001
  base address 2 =              0x48000000
  base address 3 =              0x00000000
  base address 4 =              0x00000000
  base address 5 =              0x00000000
  cardBus CIS pointer =         0x00000000
  sub system vendor ID =        0x174b
  sub system ID =               0x7c25
  expansion ROM base address =  0x00000000
  interrupt line =              0xff
  interrupt pin =               0x01
  min Grant =                   0x08
  max Latency =                 0x00
=> md.l 0x48000000 10
48000000: 00000000 00000000 00000000 00000000    ................
48000010: 00000000 00000000 00000000 00000000    ................
48000020: 00000000 00000000 00000000 00000000    ................
48000030: 41400f88 10000000 00000000 00000000    A at ..............
=> md.l 0x50000000 10
50000000: 00000000 00000000 00000000 00000000    ................
50000010: 00000000 00000000 00000000 00000000    ................
50000020: 00000000 00000000 00000000 00000000    ................
50000030: 41400f88 10000000 00000000 00000000    A at ..............
=> md.l 0x40000000 10
40000000:Bus Fault @ 0x03f95fb8, fixup 0x00000000
Machine check in kernel mode.
Caused by (from msr): regs 03f53b48 Unknown values in msr
NIP: 03F95FB8 XER: 00000000 LR: 03F95E90 REGS: 03f53b48 TRAP: 0200 DAR:
03F53F84
MSR: 00001000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00

GPR00: 03F53C38 03F53C38 FFFFBFB3 00000000 03F53B10 00000010 FFFFFFFE
00000007
GPR08: 00000001 00000800 00000000 FFFFFFFF 00000030 FFFFFFFF 03FBA000
04F84000
GPR16: FFF7FFFB FFFFFFFE 3FFFFFFF 00000000 00000010 03F53C40 03F53C40
03F53C40
GPR24: 00000040 00000010 00000004 00000000 40000000 03F53F84 03FBAA4C
03F53C40
Call backtrace:
machine check



-- 
Paul Wujek