[U-Boot-Users] omap2420h4 u-boot debugging CCS JTAG
r-woodruff2 at ti.com
Wed Feb 2 18:54:34 CET 2005
As long as you have set your SDR and GPMC timings correctly you can load
into DDR to start your work. Do know that the code will skip Clock and
DDR init then.
> Yes. I am running from SDRAM. And loading the "elf"
> through CCS.
> Is there anything specific you are expecting for the
> gel files to do it?
Generally, I and have the gel file do nothing, and load directly into
SRAM for initial debugging. Then try it from SDRAM, then finally from
flash. I've had good success stepping everything with a Lauterbach
> And in debugging the new cvs code, it gives me
> following values for the registers after executing the
> following instruction:
> 80E80554 E59FD024 LDR R13, 0x80E80580
You providing the info that SP (R13) = 0x0 confuses me. Is your working
SP really 0, or is it 0x4020FFC. You should be in SVC mode, so I bet
its 0x4020FFFC, which would be correct. Why do you provide the 0 info,
is this after the fatal abort, perhaps?
> SP(R13) : 0x00000000
> R13_SVC : 0x4020FFFC
> value at 0x80E80580 is 0x4020FFFC.
> But the next instruction
> 80E80558 E58DC000 STR R12, [R13]
If R13 as seen in your register has a 0 in it, then your crash is
expected (originally, I thought this was your case due to a memory or
image mis-configuration). If it has 0x4020FFFC in it, then it shouldn't
If it crashed with 0x4020FFFC, I'd say you are using an OLD version of
CCS which for some unknown reason needed a different driver to access
SRAM. Other emulators I've used didn't have this issue, but I did hear
that some version of CCS did.
So update your CCS. Or ask them for the magic driver which allows you
to access SRAM.
You will likely have some crashes due to needed changes in the code, but
this is not one of them. It is likely a tool issue.
I don't have the same emulator you are using so I can't really help out
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