[U-Boot-Users] Cache issue on MPC8xx

[Qichen Huang]

Hi,
I want to apply some simple tests on MPC855T and need to turn on both
instruction- and data-cache. I have used the codes in cpu/mpc8xx/start.S(as
follows), but it crashes while trying to write IDC_ENABLE to DC_CST. Do I
have to enable the MMU first? If so,
how? I have tried the code in
linuxppc_2_4_devel/arch/ppc/kernel/head_8xx.S, it also crashes while
trying to write MSR_DR|MSR_IR to msr.

Any ideas? Thanks!

Qichen


/* ************** dcache_enable in start.S ************ */
.globl dcache_enable
dcache_enable:
#if 0
SYNC
#endif
#if 1
lis r3, 0x0400 /* Set cache mode with MMU off */
mtspr MD_CTR, r3
#endif

lis r3, IDC_INVALL at h
mtspr DC_CST, r3
#if 0
lis r3, DC_SFWT at h
mtspr DC_CST, r3
#endif
lis r3, IDC_ENABLE at h
mtspr DC_CST, r3
blr

/* ************ turn_on_mmu in head_8xx.S *********** */
bl initial_mmu

/* We now have the lower 8 Meg mapped into TLB entries, and the caches
* ready to work.
*/

turn_on_mmu:
mfmsr r0
ori r0,r0,MSR_DR|MSR_IR
mtspr SRR1,r0
blr

initial_mmu:
tlbia /* Invalidate all TLB entries */
#ifdef CONFIG_PIN_TLB
lis r8, MI_RSV4I at h
ori r8, r8, 0x1c00
#else
li r8, 0
#endif
mtspr MI_CTR, r8 /* Set instruction MMU control */

#ifdef CONFIG_PIN_TLB
lis r10, (MD_RSV4I | MD_RESETVAL)@h
ori r10, r10, 0x1c00
mr r8, r10
#else
lis r10, MD_RESETVAL at h
#endif
#ifndef CONFIG_8xx_COPYBACK
oris r10, r10, MD_WTDEF at h
#endif
mtspr MD_CTR, r10 /* Set data TLB control */

/* Now map the lower 8 Meg into the TLBs. For this quick hack,
* we can load the instruction and data TLB registers with the
* same values.
*/
lis r8, KERNELBASE at h /* Create vaddr for TLB */
ori r8, r8, MI_EVALID /* Mark it valid */
mtspr MI_EPN, r8
mtspr MD_EPN, r8
li r8, MI_PS8MEG /* Set 8M byte page */
ori r8, r8, MI_SVALID /* Make it valid */
mtspr MI_TWC, r8
mtspr MD_TWC, r8
li r8, MI_BOOTINIT /* Create RPN for address 0 */
mtspr MI_RPN, r8 /* Store TLB entry */
mtspr MD_RPN, r8
lis r8, MI_Kp at h /* Set the protection mode */
mtspr MI_AP, r8
mtspr MD_AP, r8

/* Map another 8 MByte at the IMMR to get the processor
* internal registers (among other things).
*/
#ifdef CONFIG_PIN_TLB
addi r10, r10, 0x0100
mtspr MD_CTR, r10
#endif
mfspr r9, 638 /* Get current IMMR */
andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */

mr r8, r9 /* Create vaddr for TLB */
ori r8, r8, MD_EVALID /* Mark it valid */
mtspr MD_EPN, r8
li r8, MD_PS8MEG /* Set 8M byte page */
ori r8, r8, MD_SVALID /* Make it valid */
mtspr MD_TWC, r8
mr r8, r9 /* Create paddr for TLB */
ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
mtspr MD_RPN, r8

#ifdef CONFIG_PIN_TLB
/* Map two more 8M kernel data pages.
*/
addi r10, r10, 0x0100
mtspr MD_CTR, r10

lis r8, KERNELBASE at h /* Create vaddr for TLB */
addis r8, r8, 0x0080 /* Add 8M */
ori r8, r8, MI_EVALID /* Mark it valid */
mtspr MD_EPN, r8
li r9, MI_PS8MEG /* Set 8M byte page */
ori r9, r9, MI_SVALID /* Make it valid */
mtspr MD_TWC, r9
li r11, MI_BOOTINIT /* Create RPN for address 0 */
addis r11, r11, 0x0080 /* Add 8M */
mtspr MD_RPN, r8

addis r8, r8, 0x0080 /* Add 8M */
mtspr MD_EPN, r8
mtspr MD_TWC, r9
addis r11, r11, 0x0080 /* Add 8M */
mtspr MD_RPN, r8
#endif

/* Since the cache is enabled according to the information we
* just loaded into the TLB, invalidate and enable the caches here.
* We should probably check/set other modes....later.
*/
lis r8, IDC_INVALL at h
mtspr IC_CST, r8
mtspr DC_CST, r8
lis r8, IDC_ENABLE at h
mtspr IC_CST, r8
#ifdef CONFIG_8xx_COPYBACK
mtspr DC_CST, r8
#else
/* For a debug option, I left this here to easily enable
* the write through cache mode
*/
lis r8, DC_SFWT at h
mtspr DC_CST, r8
lis r8, IDC_ENABLE at h
mtspr DC_CST, r8
#endif
blr
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